Search NASA⌕ Search

SEARCH · Search NASA

Results for “bipolar transistor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Thermal Assessment and In-Situ Monitoring of Insulated Gate Bipolar Transistors in Power Electronic Modules: Preprint

Insulated gate bipolar transistor (IGBT) power modules are devices commonly used for switching of high voltages and currents. Usage and environmental conditions can cause these power modules to degrade over time, and this gradual process may eventually lead to catastrophic failure of the device. This degradation process may cause some early performance symptoms related to the state of health of the power module, making it possible to detect reliability degradation of the IGBT module. Testing can be used to accelerate this process, permitting a rapid determination of whether specific declines in device reliability can be characterized. In this study, thermal cycling was conducted on multiple power modules simultaneously in order to assess the effect of thermal cycling on the degradation of the power module. In-situ monitoring of temperature was performed from inside each power module using high temperature thermocouples. Device imaging and characterization was performed along with temperature data analysis, to assess failure modes and mechanisms within the power modules. While the experiment was aimed to assess the potential damage effects of thermal cycling on die attach, results indicated that wirebond degradation was the life limiting failure mechanism.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2022

Progress in three-terminal heterojunction bipolar transistor solar cells

Conventional solar cells, including multijunction solar cells, are based on pn junctions as building blocks. In contrast, the three-terminal heterojunction bipolar transistor solar cell (3T-HBTSC) explores the use of a bipolar transistor structure to build a solar cell. The limiting efficiency of this transistor structure equals that of a double-junction solar cell. However, since the 3T-HBTSC does not require tunnel junctions, its minimal structure has only three semiconductor layers, while the minimal structure of a double junction solar cell has six. This work reviews the operation principles of this solar cell and the steps carried out towards its practical implementation. Experimental results on a GaInP/GaAs HBTSC prototype with bottom interdigitated contacts are presented.

14 SOLAR ENERGY↗
DOE OSTI2020

Demonstrating the GaInP/GaAs Three-Terminal Heterojunction Bipolar Transistor Solar Cell

The three-terminal heterojunction bipolar transistor solar cell (HBTSC) concept enables the realization of a monolithic double-junction device with individual current extraction. We present an HBTSC realized by a heterojunction of GaInP and GaAs. The one-sun open-circuit voltage (V OC ) of the top and bottom junctions are 1.33 V and 0.99 V, respectively, while fill factors (FF) are above 80%. At one-sun illumination, reducing one junction's bias from V OC to maximum power point degrades the performance of the other junction only slightly (<; 0.5% efficiency loss). These results demonstrate the potential of the HBTSC concept to produce high-efficiency independently connected double-junction solar cells.

14 SOLAR ENERGY↗
DOE OSTI2021

Inverted GaInP/GaAs Three-Terminal Heterojunction Bipolar Transistor Solar Cell

Here we present the experimental results of an inverted three-terminal heterojunction bipolar transistor solar cell (HBTSC) made of GaInP/GaAs. The inverted growth and processing enables contacting the intermediate layer from the bottom, which increases the cell performance by reducing shadow factor and series resistance at the same time. With this prototype we show that an inverted processing of a three-terminal solar cell is feasible and pave the way for the application of epitaxial lift-off, substrate reuse and mechanical stacking to the HBTSC which can eventually lead to a low-cost high-efficiency III-V-on-Si HBTSC technology.

41 EE - Solar Energy Technologies Office (EE-4S)↗
DOE OSTI2023

Bipolar transistor structure with collector on polycrystalline isolation layer and methods to form same

Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

Holt, Judson R.↗
DOE OSTI2023

Low-Frequency Noise and Deep Level Transient Spectroscopy in n-p-n Si Bipolar Junction Transistors Irradiated with Si Ions

The properties of defects in n-p-n Si bipolar junction transistors (BJTs) caused by 17 MeV Si ions are investigated via current-voltage, low-frequency noise, and deep-level transient spectroscopy (DLTS) measurements. Four prominent radiation-induced defects in the base-collector junction of these transistors are identified via DLTS. At least two defect levels are observed in temperature-dependent low-frequency 1/ f noise measurements, one that is similar to a prominent defect in DLTS and another that is not. Defect microstructures are discussed. Here our results show that DLTS and 1/ f noise measurements can provide complementary information about defects in linear bipolar devices.

42 ENGINEERING↗
DOE OSTI2024

Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors

Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.

42 ENGINEERING↗
DOE OSTI2021

Compensated Contacts for Three-Terminal Transistor Solar Cells

The heterojunction bipolar transistor solar cell (HBTSC) is an alternative to conventional double-junction solar cells that combines the advantages of three-terminal architectures with a compact design. A critical part of the HBTSC fabrication is the implementation of the middle contact, the one associated to the base layer in the transistor structure, because this layer can be damaged by the diffusion of metallic species during contact annealing. As a solution we propose to implement a "compensated contact", that is, to leave a thin (< 200 nm) portion of emitter or collector between the base layer and the contact metals and compensate its doping during contact annealing. Using an Au/Zn/Au metal structure to compensate a 150 nm thick portion of the collector, we obtain a specific contact resistance ~8 10-4 ..omega.. cm2. This value is fairly invariant for annealing temperatures between 400 and 460 degrees C and annealing times between 2 and 5 minutes, and it does not improve by adding Pd to the metallic stack. Optimizing the compensated contact technology opens the path to the realization of III-V-material-based HBTSCs with open-circuit voltages and fill factors comparable to those of conventional multijunction architectures.

contact resistance↗
DOE OSTI2026

Two-Phase Cooling for High Packaging Density Planar Inverter: Cooperative Research and Development Final Report, CRADA Number CRD-15-00592

The project objective was to utilize two-phase heat transfer to enable compact and power-dense inverters. The high heat transfer capacity and near isothermal characteristics of two-phase cooling can enable higher power densities, reducing the size and cost of the power electronics system. This project focused on developing efficient, passive (no pump or compressor) two-phase cooling strategies that consist of an air-cooled condenser and evaporator. This report describes the modeling work conducted to design the evaporator and air-cooled condenser for a prototype inverter development work underway in the John Deere. Prototypes of the final evaporator and condenser designs were then fabricated via 3D printing for testing. Experiments on the evaporator confirmed that this component can meet the heat load and junction temperatures requirements for Si IGBT (insulated-gate bipolar transistor) inverter. Experiments with the air-cooled condenser were not possible due to leaks through the condenser walls.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2024

Solid state protective smart plug device

A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.

Shen, Zheng↗
DOE OSTI2021

Correlation Between Corrugation-Induced Flexoelectric Polarization and Conductivity of Low-Dimensional Transition Metal Dichalcogenides

The tunability of polar and semiconducting properties of low-dimensional transition metal dichalcogenides (TMDs) have propelled them to the forefront of fundamental and applied physical research. These materials can vary their electrophysical properties from nonpolar to ferroelectric, and from direct-band semiconducting to metallic. In addition to classical controlling factors, such as field effect, composition, and doping, new degrees of freedom emerge in TMDs due to the curvature-induced electron redistribution and the associated changes in electronic properties. Here we theoretically explore the elastic and electric fields, flexoelectric polarization and free charge density for a TMD nanoflake placed on a rough substrate with a sinusoidal corrugation profile. Finite element modelling results for different flake thickness and corrugation depth yield insights into the flexoelectric nature of the out-of-plane electric polarization and establish the unambiguous correlation between the polarization and static conductivity modulation. The modulation is caused by the coupling between the deformation potential and inhomogeneous elastic strains, which evolve in the TMD nanoflake due to the adhesion between the flake surface and corrugated substrate. We reveal a pronounced maximum in the thickness dependences of the electron and hole conductivity of MoS 2 and MoTe 2 nanoflakes placed on a corrugated substrate, which opens the way for the optimization of their geometry towards significant improvement in their polar and electronic properties, necessary for advanced applications in nanoelectronics and memory devices. Specifically, the obtained results can be useful for the development of nanoscale straintronic devices based on the bended MoS 2 , MoTe 2 , and MoSTe nanoflakes, such as diodes and bipolar transistors with a bending-controllable sharpness of p-n junctions.

42 ENGINEERING↗
DOE OSTI2022

A Current Limiting Control Strategy for Single-Loop Droop-Controlled Grid-Forming Inverters Under Balanced and Unbalanced Faults

Existing studies reporting current limiting control strategies for grid-forming inverters primarily focus on grid-forming inverters that use a multi-loop control structure. This study reports a current limiting control for grid-forming inverters that uses a single-loop control structure. The proposed current limiting control was implemented at the pulse width modulation (PWM) control layer to guarantee a rapid response. Once an overcurrent caused by severe faults is detected, the proposed control strategy immediately blocks relevant insulated-gate bipolar transistors (IGBTs) using a hysteresis loop, ensuring that the overcurrent is limited within a few PWM cycles. After the fault is cleared, the inverter seamlessly transfers back to droop control mode to maintain stability. The current limiting control has been tested in a microgrid environment operating in the OPAL-RT platform. Study results show that the control strategy can effectively limit the overcurrent under both balanced and unbalanced faults and can maintain system transient stability after the fault is cleared.

Du, Wei↗
DOE OSTI2020

A Simple Physical Model for Three-Terminal Tandem Cell Operation

We present a simple physical model that explains the device operation of a three-terminal (3T) IBC Si bottom cell platform that enables an efficient 3T tandem. If the IBC cell has two p-n junctions and one high-low junction (bipolar transistor), the two p-n junctions strongly interact via minority carrier diffusion in the base. In a two-BSF junction and one p-n junction IBC platform (single emitter), the BSF terminals interact via ohmic majority carrier current in the base. This interaction creates wide 'generating' power islands in the 2D current J 1 J 2 plane. The area and shape of these islands are determined by dissipative losses in the wafer base and in the cell contacts. Both positive and negative terminal currents are allowed for 3T operation, thus enabling both the top and bottom cells to operate at their full light currents. This opens new possibilities for 3T use in modules.

14 SOLAR ENERGY↗