Bypass switching for cellular cascades
One dimensional cellular logic arrays fault circumvention by bypass switching out defective cells in cascade
Kautz, W. H.↗
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Cascaded transformerless DC-DC voltage amplifier with optically isolated switching devices
A very high voltage amplifier is provided in which plural cascaded banks of capacitors are switched by optically isolated control switches so as to be charged in parallel from the preceding stage or capacitor bank and to discharge in series to the succeeding stage or capacitor bank in alternating control cycles. The optically isolated control switches are controlled by a logic controller whose power supply is virtually immune to interference from the very high voltage output of the amplifier by the optical isolation provided by the switches, so that a very high voltage amplification ratio may be attained using many capacitor banks in cascade.
Sridharan, Govind↗
Pulse switching for high energy lasers
A saturable inductor switch for compressing the width and sharpening the rise time of high voltage pulses from a relatively slow rise time, high voltage generator to an electric discharge gas laser (EDGL) also provides a capability for efficient energy transfer from a high impedance primary source to an intermediate low impedance laser discharge network. The switch is positioned with respect to a capacitive storage device, such as a coaxial cable, so that when a charge build-up in the storage device reaches a predetermined level, saturation of the switch inductor releases or switches energy stored in the capactive storage device to the EDGL. Cascaded saturable inductor switches for providing output pulses having rise times of less than ten nanoseconds and a technique for magnetically biasing the saturable inductor switch are disclosed.
Laudenslager, J. B.↗
Monolithic Microwave Switching Matrix
Gallium arsenide integrated-circuit chip switches any of three microwave input signals to any of three output ports. Measuring 4.9 mm on side, chip contains nine field-effect transistor (FET) crosspoint switches. Housed in custom-designed package with standard connectors for easy integration into system. FET's on chip operated as passive switches and consume no static power and insignificant amounts of switching power. Chip module cascades with similar modules into large arrays handling as many as 100 inputs and 100 outputs. Applications include switching and routing vast amounts of data between computers at extremely high speed. On communications satellite, chip switches microwave signals to and from Earth stations and other satellites.
Fujikawa, Gene↗
Bipolar-FET combinational power transistors for power conversion applications
Four bipolar-FET (field-effect transistor) combinational transistor configurations are compared from the application point of view. The configurations included are FET-Darlington (cascade), emitter-open switch (cascode), parallel configuration, and FET-gated bipolar transistors (FGT).
Chen, D. Y.↗
Design of an Auto-zeroed, Differential, Organic Thin-film Field-effect Transistor Amplifier for Sensor Applications
Organic strain gauge and other sensors require high-gain, precision dc amplification to process their low-level output signals. Ideally, amplifiers would be fabricated using organic thin-film field-effect transistors (OTFT's) adjacent to the sensors. However, OTFT amplifiers exhibit low gain and high input-referred dc offsets that must be effectively managed. This paper presents a four-stage, cascaded differential OTFT amplifier utilizing switched capacitor auto-zeroing. Each stage provides a nominal voltage gain of four through a differential pair driving low-impedance active loads, which provide common-mode output voltage control. p-type pentacence OTFT's are used for the amplifier devices and auto-zero switches. Simulations indicate the amplifier provides a nominal voltage gain of 280 V/V and effectively amplifies a 1-mV dc signal in the presence of 500-mV amplifier input-referred dc offset voltages. Future work could include the addition of digital gain calibration and offset correction of residual offsets associated with charge injection imbalance in the differential circuits.
large-area electronics↗
Evaluation of diffuse-illumination holographic cinematography in a flutter cascade
Since 1979, the Lewis Research Center has examined holographic cinematography for three-dimensional flow visualization. The Nd:YAG lasers used were Q-switched, double-pulsed, and frequency-doubled, operating at 20 pulses per second. The primary subjects for flow visualization were the shock waves produced in two flutter cascades. Flow visualization was by diffuse-illumination, double-exposure, and holographic interferometry. The performances of the lasers, holography, and diffuse-illumination interferometry are evaluated in single-window wind tunnels. The fringe-contrast factor is used to evaluate the results. The effects of turbulence on shock-wave visualization in a transonic flow are discussed. The depth of field for visualization of a turbulent structure is demonstrated to be a measure of the relative density and scale of that structure. Other items discussed are the holographic emulsion, tests of coherence and polarization, effects of windows and diffusers, hologram bleaching, laser configurations, influence and handling of specular reflections, modes of fringe localization, noise sources, and coherence requirements as a function of the pulse energy. Holography and diffuse illumination interferometry are also reviewed.
Decker, A. J.↗
Multiple-mode reconfigurable electro-optic switching network for optical fiber sensor array
This paper reports the first switching network compatible with multimode fibers. A one-to-many cascaded reconfigurable interconnection was built. A thin glass substrate was used as the guiding medium which provides not only higher coupling efficiency from multimode fiber to waveguide but also better tolerance of phase-matching conditions. Involvement of a total-internal-reflection hologram and multimode waveguide eliminates interface problems between fibers and waveguides. The DCG polymer graft has proven to be reliable from -180 C to +200 C. Survivability of such an electrooptic system in harsh environments is further ensured. LiNbO3 was chosen as the E-O material because of its stability at high temperatures (phase-transition temperature of more than 1000 C) and maturity of E-O device technology. Further theoretical calculation was conducted to provide the optimal interaction length and device capacitance.
Chen, Ray T.↗
High isolation RF signal selection switches
A selection switch with high isolation between RF signal input terminals is achieved with a gated Schmitt trigger circuit feeding into a control NAND gate in each signal switching channel. The control NAND gates of the separate signal channels are coupled to an output terminal by a single NAND gate. The schmitt trigger circuits and all gates are implemented with Schottky transistor-transistor logic circuits having input clamping diodes. Each Schmitt trigger circuit includes two cascaded NAND gates and a feedback isolation Schottky diode between one input terminal connected to receive an RF input and another input terminal connected to receive a feedback signal from the second of the two cascaded NAND gates. Both NAND gates of the Schmitt trigger circuits are enabled by the same switch control signal which enables the control gates.
Hanna, M. F.↗
Compact programmable photonic variable delay devices
Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.
Yao, X. Steve↗
Photonic variable delay devices based on optical birefringence
Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.
Yao, X. Steve↗
Solid-state Image Sensor with Focal-plane Digital Photon-counting Pixel Array
A solid-state focal-plane imaging system comprises an NxN array of high gain. low-noise unit cells. each unit cell being connected to a different one of photovoltaic detector diodes, one for each unit cell, interspersed in the array for ultra low level image detection and a plurality of digital counters coupled to the outputs of the unit cell by a multiplexer(either a separate counter for each unit cell or a row of N of counters time shared with N rows of digital counters). Each unit cell includes two self-biasing cascode amplifiers in cascade for a high charge-to-voltage conversion gain (greater than 1mV/e(-)) and an electronic switch to reset input capacitance to a reference potential in order to be able to discriminate detection of an incident photon by the photoelectron (e(-))generated in the detector diode at the input of the first cascode amplifier in order to count incident photons individually in a digital counter connected to the output of the second cascade amplifier. Reseting the input capacitance and initiating self-biasing of the amplifiers occurs every clock cycle of an integratng period to enable ultralow light level image detection by the may of photovoltaic detector diodes under such ultralow light level conditions that the photon flux will statistically provide only a single photon at a time incident on anyone detector diode during any clock cycle.
Fossum, Eric R.↗
Switched-Polarization Birefringent Optical Delay Lines
Controllable birefringent optical delay lines proposed for use in photonically controlling phases of signals in radiating elements of phased-array antennas. Features low optical insertion losses and made very compact, enabling high packing densities where multiple delay channels needed. Polarization switched in segments to adjust overall delay. Furthermore, two or more delay lines cascaded increases delay-adjustment range.
Yao, Xiaotian Steve↗
Design of microstrip components by computer
A number of computer programs are presented for use in the synthesis of microwave components in microstrip geometries. The programs compute the electrical and dimensional parameters required to synthesize couplers, filters, circulators, transformers, power splitters, diode switches, multipliers, diode attenuators and phase shifters. Additional programs are included to analyze and optimize cascaded transmission lines and lumped element networks, to analyze and synthesize Chebyshev and Butterworth filter prototypes, and to compute mixer intermodulation products. The programs are written in FORTRAN and the emphasis of the study is placed on the use of these programs and not on the theoretical aspects of the structures.
Cisco, T. C.↗
A quasi-passive CMOS pipeline D/A converter
A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.
Wang, Fong-Jim↗
Intermittent Flow Regimes in a Transonic Fan Airfoil Cascade
A study was conducted in the NASA Glenn Research Center linear cascade on the intermittent flow on the suction surface of an airfoil section from the tip region of a modern low aspect ratio fan blade. Experimental results revealed that, at a large incidence angle, a range of transonic inlet Mach numbers exist where the leading-edge shock-wave pattern was unstable. Flush mounted high frequency response pressure transducers indicated large local jumps in the pressure in the leading edge area, which generates large intermittent loading on the blade leading edge. These measurements suggest that for an inlet Mach number between 0.9 and 1.0 the flow is bi-stable, randomly switching between subsonic and supersonic flows. Hence, it appears that the change in overall flow conditions in the transonic region is based on the frequency of switching between two stable flow states rather than on the continuous increase of the flow velocity. To date, this flow behavior has only been observed in a linear transonic cascade. Further research is necessary to confirm this phenomenon occurs in actual transonic fans and is not the byproduct of an endwall restricted linear cascade.
Lepicovsky, J.↗
Single phase dynamic CMOS PLA using charge sharing technique
A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.
Dhong, Y. B.↗
Programmable synaptic chip for electronic neural networks
A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.
Moopenn, A.↗