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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Electronics for Extreme Environments

Most of the NASA missions involve extreme environments comprising radiation and low or high temperatures. Current practice of providing friendly ambient operating environment to electronics costs considerable power and mass (for shielding). Immediate missions such as the Europa orbiter and lander and Mars landers require the electronics to perform reliably in extreme conditions during the most critical part of the mission. Some other missions planned in the future also involve substantial surface activity in terms of measurements, sample collection, penetration through ice and crust and the analysis of samples. Thus it is extremely critical to develop electronics that could reliably operate under extreme space environments. Silicon On Insulator (SOI) technology is an extremely attractive candidate for NASA's future low power and high speed electronic systems because it offers increased transconductance, decreased sub-threshold slope, reduced short channel effects, elimination of kink effect, enhanced low field mobility, and immunity from radiation induced latch-up. A common belief that semiconductor devices function better at low temperatures is generally true for bulk devices but it does not hold true for deep sub-micron SOI CMOS devices with microscopic device features of 0.25 micrometers and smaller. Various temperature sensitive device parameters and device characteristics have recently been reported in the literature. Behavior of state of the art technology devices under such conditions needs to be evaluated in order to determine possible modifications in the device design for better performance and survivability under extreme environments. Here, we present a unique approach of developing electronics for extreme environments to benefit future NASA missions as described above. This will also benefit other long transit/life time missions such as the solar sail and planetary outposts in which electronics is out open in the unshielded space at the ambient space temperatures and always exposed to radiation. Additional information is contained in the original extended abstract.

Patel, J. U.↗
NASA NTRS2007

Radiation Hardened Electronics for Extreme Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches.

Keys, Andrew S.↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfgurable devices were exposed to, and degraded by, high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms.

evolutionary search algorithms↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS2018

Evaluation of Commercial-Off-The-Shelf (COTS) Electronics for Extreme Cold Environments

Deep space and Icy Moon missions (Titan, Enceladus, Ceres, Europa, & Ganymede) will need qualified extreme environment capable components for electronic systems located in extremities of their rovers and spacecraft. Commercial off the shelf (COTS) components would be advantageous to use for some aspects of such projects, given that they are easier to procure and offer a broad range of functionalities. Furthermore, theoretical and experimental data suggest that many COTS parts are capable of operation, and not just storage, at temperatures well beyond the manufacturer specified temperature limits. To help address the challenges presented at near cryogenic temperatures, a COTS selection knowledge base is being developed to estimate the performance of COTS components within cold environments. The knowledge base captures queries from a range of information sources such as cold functionality test results for part types and families, theoretical and experimental literature reviews and key findings are summarized here. In addition, a selection of components are planned to be examined for their performance to near cryogenic temperatures to generate a methodology for identification and verification of the COTS candidates. As the qualification of COTS parts for extreme environments can be very costly, this knowledge base can serve to reduce qualification time and cost by pre-selecting and limiting candidates.

Mojarradi, Mohammad↗
DOE OSTI2026

Epitaxy of Beta-Ga2O3 on Highly-Offcut (Greater than 10 Degrees) Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction.1 These films show step-flow growth from (-201) step-edges and high electron mobility. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (4.8 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe 100% reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.

36 MATERIALS SCIENCE↗
NASA NTRS2016

High Temperature Boost (HTB) Anode Power Supply for a Modular and Scalable Power Processing Unit

A concept of a modular and scalable 10kW to 80kW High Temperature Boost (HTB) Power Processing Unit (PPU) capable of operating at temperatures beyond the standard military temperature range was proposed for solar electric in-space propulsion. Within the PPU, the Anode Power Supply (APS) module is a 10kW modular power stage and is the key to the HTB PPU. This paper is to present the design, development, fabrication, testing and thermal demonstration of the 10kW HTB APS. The system architecture and the paradigm shift of the HTB PPU is also to be described. In addition, the extreme environments electronic and packaging technologies are addressed as the fundamental technology path. The HTB PPU is intended for power processing in the area of space solar electric propulsion, where reduction of in-space mass and volume are desired, and sometimes even critical, to achieve the goals of future space flight missions. The concept of the HTB PPU can also be applied to other extreme environment applications, such as geothermal and petroleum deep-well drilling, where higher temperature operation is required.

Carr, Gregory A.↗
NASA NTRS2005

Re-Configurable Electronics Characterization under Extreme Thermal Environment

The need for reconfigurable electronics is driven by requirements to survive longer missions and harsher environments. It is possible to compensate for degradations in Extreme Environments (EE). EE has effect on electronics: circuits are designed to exploit device characteristics and when a certain temperature or radiation range is exceeded the circuit function gradually degrades. It is possible to employ Hardening by reconfiguration (HBR) to mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. In this manner degraded components can be salvaged, and completely damaged components can be bypassed. The challenge of conventional design is replaced with that of designing a recover process that automatically performs the (re) design in place of the designer. The objective of testing a Digital Signal Processor (DSP) under the extreme temperatures was to determine the lowest temperature at which the DAP can operate. The objective of testing a Xilinx VirtexII Pro FPGA board was to initially find our whether the evaluation board and the FPGA would survive and continue at temperature ranges from -180 C, and 120 C. The Virtex II functioned correctly at the temperatures tested. The next test was done on the GM-C filter building block using the same temperature range as the Virtex II. The current lower and upper limits were shown to be reduced as the temperature gets lower. The device function can be recovered by increasing the Vb from .08V to .85V. The negative and positive saturation voltages increases as the temperature gets higher. The function of the device can be recovered by decreasing the Vb from .8V to around .75V. The next test was performed to test the recovery of the GmC low pass filter through Vb in a filter circuit. The test indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures.

reliability↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2022

Silicon Carbide Sensors and Electronics Technology for Extreme Environments: Opportunities for Nuclear Power Applications

Over the past five decades, NASA Glenn Research Center had been advancing the development of single crystal silicon carbide growth, sensors and electronics device technologies, culminating in the recent demonstration of Micro-Electro-Mechanical Systems scale batch fabricated pressure sensors operating at 800 °C and integrated circuit electronics with demonstrated durability of over 1000 hours at 500 °C. As a result of the progress made in demonstrating the high temperature capability of the technology, insertion into actual operational environments, such as in jet engines and planet Venus, are in progress. The high temperature, near inert surface chemistry, and radiation hardness attributes of SiC, coupled with the relative maturation of the device batch microfabrication, contact metallization, and packaging technologies, make the material a prime candidate for use as part of future advanced nuclear reactor instrumentation and control strategy. Hence the current research efforts at NASA Glenn are aimed toward harnessing these attributes in developing SiC sensors and electronics for nuclear reactor applications, potentially for future Lunar/Martian nuclear power and the emerging terrestrial micro nuclear power plants.

silicon carbide↗
NASA NTRS2005

Re-configurable electronics behavoir under extreme thermal environment

This paper focuses on analog/digital electronics at low-temperatures. The experiments cover separate tests of the whole Evolvable Hardware system: the Evolutionary Processor (the DSP in the SABLE system), Xilinx Virtes II Pro FPGA evaluation board, and the Reconfigurable analog array components tested at low and high temperatures.

Field Programmable Transistor Arrays (FPTA)↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗