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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.
The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.
The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.
A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states corresponds to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.
A system is for a plurality of different electric load types. The system includes a plurality of sensors structured to sense a voltage signal and a current signal for each of the different electric loads; and a processor. The processor acquires a voltage and current waveform from the sensors for a corresponding one of the different electric load types; calculates a power or current RMS profile of the waveform; quantizes the power or current RMS profile into a set of quantized state-values; evaluates a state-duration for each of the quantized state-values; evaluates a plurality of state-types based on the power or current RMS profile and the quantized state-values; generates a state-sequence that describes a corresponding finite state machine model of a generalized load start-up or transient profile for the corresponding electric load type; and identifies the corresponding electric load type.
Computer programs are often viewed as collections of functions – each function has parameters (inputs) and computes a return value, and each has potential side effects that modify program state (outputs). In this research, a Sandia symbolic execution tool designed to support “human-in-the-loop” analysis was modified to automatically create “function summaries,” and a new tool, “diaboolical,” was created to support enhancing readability of the summary using a novel approach to bit-vector simplification that leverages logic synthesis and tautologies. For this effort, students at Auburn University created several finite state machines (FSMs) to serve as exemplars for high-consequence systems. Function summaries for each of the machines were obtained, and then portions of the summaries were simplified using both diaboolical and the simplification procedure of a popular SMT solver. A comparison of the results shows that diaboolical can often produce smaller function summaries, with expression length improvements over the unsimplified function summaries ranging from 0% to 90% for diaboolical and 0% to 65% for the SMT solver, though diaboolical had a significantly greater cost in time. Diaboolical was evaluated against a collection of “arbitrary” C-code as well as FSM exemplars, and for both datasets it achieved an approximately 10% improvement in expression length compared to simplifications that could be obtained using existing techniques. Function summaries can assist assurance efforts that evaluate existing systems and their executable code. A smaller function summary is likely easier for humans to understand and could thus increase the ability and efficacy of assurance practices centered around the analysis of executable artifacts.
Event-driven contexts in manufacturing occur pervasively as a result of interactions among involved entities such as machines, workers, materials, and environment. One of the primary tasks in smart manufacturing is to derive a context-aware system conveniently incorporating worker knowledge for generating timely actionable intelligence for workers on factory floor and supervisors to respond. In this paper, we propose to design a human-and-machine interaction recognition framework by using a causality concept to collect contextual data for classifications of normal and abnormal machine operations. The causes and effects are between workers and machines for this initial research. To apply the causality to recognize worker interactions, initially a reliable way to identify the states of machines is necessary. The proposed contextual sensor system, consisting of a power meter for measuring machine operation conditions, a visual camera for capturing worker and machine interactions via a finite state machine model, and an algorithm for determining power signatures of individual components via energy disaggregation is implemented on semiconductor fabrication machines (manual or PLC controlled) each with multiple components. The experiment results demonstrate its context extraction capability such as components states and their corresponding energy usage in real time as well as its ability to identify anomalous operation conditions.
The Testsofa is used to explore the functioning of an integrated circuit. It characterizes pin functions via pin profiling, then serves as an interface to a Boss server which creates a finite state machine (FSM) model using branch exploration. This exploration is done via a stimulus/response process, which will be explained in the Internal Logic Testing section.
Accurate estimation of dynamic states (such as synchronous machine rotor angle and speed) is critical for monitoring and controlling transient stability. Extended Kalman filter (EKF)--based approaches have been developed for estimating dynamic states. In order to improve the EKF's performance in estimating dynamic states of a synchronous machine, this paper proposes a multi-step adaptive interpolation (MSAI) approach to achieve balance between estimation accuracy and computational time. This approach consists of three major steps. First, two indexes are calculated to quantify the nonlinearity of the state transition function and measurement function, respectively. Second, based on the nonlinearity indexes, the interpolation factor is determined using a finite state machine model. And finally, to mitigate the negative impact of nonlinearity on the estimation accuracy, pseudo-measurements are added between consecutive measurements through linear interpolation. A simple example is used to validate the proposed nonlinear indexes. The two-area four-machine system and 16-machine 68-bus system are used to evaluate the effectiveness of the proposed MSAI approach. It is shown through the Monte-Carlo method that the estimation accuracy can be improved through interpolation. In addition, a good trade-off between estimation accuracy and computational time can be achieved effectively through the proposed MSAI approach.
Automation is a critical tenet of reactor plant operations as reliance on nuclear energy increases. Nuclear power plants require a large workforce which does not scale with output; that is, the cost per megawatt increases as reactor output becomes smaller. The economic viability of advanced reactors, particularly small modular reactors (SMRs) and microreactors, requires a significantly reduced onsite workforce. The logical solution is establishing a systematic process of elimination of reliance on human operators, and to the extent possible, replacing these actions with automated functions. In this paper, we propose a method for such transformation to establish a robust technical basis to enable transition to autonomy. Our method is based on finite state automata (FSA)—also known as finite state machines (FSMs). Relying on this method allows us to exploit the rich set of mathematical proofs available in the field of regular languages. FSA are one of the mathematical tools to model discrete event systems (DES). These properties are applied to produce an automated startup controller for the Massachusetts Institute of Technology Research Reactor (MITR). The startup procedure is captured in terms of discrete changes from one state to another while an independent supervisory control system directs the sequence of states and alerts a human in the event of an abnormal operation. First, the design and behavior of the MITR rod control system were modeled in Simulink. Then, the startup procedure was applied to the rod control system and the DES performed a startup by procedurally withdrawing rods to the subcritical position. The simulation also stops rod motion in response to an uncontrollable event and restarts rod motion once the event has been cleared.
The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.
This paper reports on the extension of our amplitude-based resonant magnetic perturbation (RMP) edge localized mode (ELM) controller to support phasing control (relative toroidal phases of RMP waveforms between rows of coils), multiple toroidal mode numbers, and new ‘jump’ and ‘probing’ strategies, all deployed on KSTAR and DIII-D. By treating the control algorithm as device-independent and adjusting only the real-time interfaces to sensors and power supplies, we have confirmed that the same finite state machine—based feedback logic can be ported between machines with minor modifications. In experiments using n = 2 RMPs on KSTAR and n = 3 on DIII-D, the controller successfully modulated RMP amplitudes in real time to sustain ELM suppression while minimizing confinement degradation. Phasing control broadened the suppression window, as it permitted the system to avoid locked-mode regions and safely access ELM-free conditions. A rotating RMP phasing scheme, integrated into the same framework, distributes divertor heat loads more uniformly, making it a promising strategy for protecting plasma-facing components during long discharges. New ‘jump’ and ‘probing’ techniques demonstrate the possibility for the controller to preempt imminent ELMs and refine the minimum required RMP amplitude without returning to ELMy conditions. Taken together, these upgrades enable extended ELM-free operation while mitigating confinement degradation, providing a practical framework for real-time ELM control in future high-performance tokamaks.
This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.
Finite State Machines (FSMs) are fundamental in both hardware design and software development. However, the reliability of FSM computations remains poorly understood. This becomes increasingly critical as the technology scaling becomes more aggressive. Existing reliability analyses are mainly designed for generic computations and are unaware of the special error tolerance characteristics in FSM computations. In this work, we introduce RelyFSM – a state-level reliability analysis framework for FSM computations. By qualitatively reasoning about the transition structures in FSM computations, RelyFSM can precisely capture their inherent error tolerance. Basically, RelyFSM takes an FSM specification as input and analyzes its reliability for a specific execution. At the core of the analysis is a set of mathematical models that accurately define the behaviors of unreliable FSM executions. Our evaluation with a spectrum of FSM benchmarks confirms the accuracy and efficiency of RelyFSM in analyzing the reliability of real-world FSM computations.
The objective of the project is to demonstrate that critical control functions can be implemented using little resources in modern microelectronics. A finite state machine (Figure 1) is implemented onto a field programmable gate array (FPGA). The functionality of the system is demonstrated by sending binary instructions to the controller. The controller transmits patterns through an LED, controls an electromechanical device, and uses pulse-width modulation (PWM) for radar functions.
A self-balanced modulation method and a closed-loop magnetic flux rebalancing control method for parallel multilevel inverters. The combination of the two methods provides for balancing of the magnetic flux of the inter-cell transformers (ICTs) of the parallel multilevel inverters without deteriorating the quality of the output voltage. In various embodiments a parallel multi-level inverter modulator is provide including a multi-channel comparator to generate a multiplexed digitized ideal waveform for a parallel multi-level inverter and a finite state machine (FSM) module coupled to the parallel multi-channel comparator, the FSM module to receive the multiplexed digitized ideal waveform and to generate a pulse width modulated gate-drive signal for each switching device of the parallel multi-level inverter. The system and method provides for optimization of the output voltage spectrum without influence the magnetic balancing.
The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).