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Results for “flip chip devices”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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6 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Noncontact excitation of multi-GHz lithium niobate electromechanical resonators

Abstract The demand for high-performance electromechanical resonators is ever-growing across diverse applications, ranging from sensing and time-keeping to advanced communication devices. Among the electromechanical materials being explored, thin-film lithium niobate stands out due to its strong piezoelectric properties and low acoustic loss. However, in nearly all existing lithium niobate electromechanical devices, the configuration is such that the electrodes are in direct contact with the mechanical resonator. This configuration introduces an undesirable mass-loading effect, producing spurious modes and additional damping. Here, we present an electromechanical platform that mitigates this challenge by leveraging a flip-chip bonding technique to separate the electrodes from the mechanical resonator. By offloading the electrodes from the resonator, our approach yields a substantial increase in the quality factor of these resonators, paving the way for enhanced performance and reliability for their device applications.

Instruments & Instrumentation↗
DOE OSTI2025

Increasing Radon Daughter Plate-out onto Superconducting Qubits

Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out onto a superconducting qubit chip can decay, releasing energy into the substrate, producing phonons. Phonon induced quasiparticles generate bit flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of Radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to finalize design for a device to increase radon plate-out.

Kay, Dax [Northwestern U.]↗
DOE OSTI2026

Increasing Radon Daughter Plate-out onto Superconducting Qubits

Radon daughter plate-out may pose a fundamental limitation to realizing large-scale superconducting quantum computers. Radon daughters plated-out on a superconducting qubit can decay, releasing energy into the substrate, producing phonons. Phonon-induced quasiparticles then generate bit-flip errors and reduce coherence times. We seek to increase plate-out on chips to enable future study of the impact of radon on coherence times. In this project, we utilize COMSOL Multiphysics simulations to visualize electric field configuration and model ion transport to finalize design of a device to increase radon plate-out on qubit chips.

Kay, Dax [Fermilab; Northwestern U.]↗
DOE OSTI2024

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole↗
DOE OSTI2025

Spin Decoherence Dynamics of Er 3+ in CeO 2 Films

Developing telecom-compatible spin-photon interfaces is essential towards scalable quantum networks. Erbium ions (Er 3+ ) exhibit a unique combination of a telecom (1.5 mu m) optical transition and an effective spin-1=2 ground state, but identifying a host that enables heterogeneous device integration while preserving long optical and spin coherence remains an open challenge. In this work, we explore the potential of Er 3+ :CeO 2 films on silicon and study the Er 3+ spin coherence, offering low nuclear spin density and the potential for on-chip integration. We demonstrate a 38.8 mu s spin coherence, which can be extended to 176.4 mu s with dynamical decoupling. Pairing experiments with cluster correlation expansion calculations, we identify spectral diffusion induced by bath Er 3+ spin flip-flops as the dominant decoherence mechanism and provide pathways to millisecond-scale coherence.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗