A simplified model of midcourse maneuver execution errors
Explore the source record for details and available documents.
ERROR↗
SEARCH · Search NASA
Results for “gate error”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Time-division multiplexer uses digital gates
Device eliminates errors caused by analog gates in multiplexing a large number of channels at high frequency. System was designed for use in aerospace work to multiplex signals for monitoring such variables as fuel consumption, pressure, temperature, strain, and stress. Circuit may be useful in monitoring variables in process control and medicine as well.
Myers, C. E.↗
Determination of optimum nonlinear systems for generalized error criteria based on the use of gate functions.
Generalization of error criteria in analysis of optimum nonlinear system
NONLINEAR SYSTEM↗
Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays
We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
error rate calculations↗
Error propagation in a digital avionic mini processor
A methodology is introduced and demonstrated for the study of error propagation from the gate to the chip level. The importance of understanding error propagation derives from its close tie with system activity. In this system the target system is BDX-930, a digital avionic multiprocessor. The simulator used was developed at NASA-Langley, and is a gate level, event-driven, unit delay, software logic simulator. An approach is highly structured and easily adapted to other systems. The analysis shows the nature and extent of the dependency of error propagation on microinstruction type, assembly level instruction, and fault-free gate activity.
Lomelino, Dale L.↗
Ultrasonic biomedical measuring and recording apparatus
A train of ultrasonic pulses is beamed into the body of an animal. Organs intercepted by the beam reflect echo pulses following each transmitted pulse. An electronic gate with a variable width and a variable time delay relative to the transmitted pulse is utilized for selecting echoes derived from other organs or portions of organs. The integral of the echo signals received within the first half of the gate period is subtracted from a corresponding integral of the echo signal received during the second half of the gate to derive an error signal for controlling the time delay of the gate. In this manner, the selected echo signal is always maintained in the center of the gate.
Lee, R. D.↗
Error propagation in a digital avionic processor: A simulation-based study
An experimental analysis to study error propagation from the gate to the chip level is described. The target system is the CPU in the Bendix BDX-930, an avionic miniprocessor. Error activity data for the study was collected via a gate-level simulation. A family of distributions to characterize the error propagation, both within the chip and at the pins, was then generated. Based on these distributions, measures of error propagation and severity were defined. The analysis quantifies the dependency of the measured error propagation on the location of the fault and the type of instruction/microinstruction executed.
Lomelino, D.↗
Radiation-Hardened Solid-State Drive
A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.
Sheldon, Douglas J.↗
Systems and methods for detecting a failure event in a field programmable gate array
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.
Ng, Tak-Kwong↗
Error-Compensated Integrate and Hold
Differencing circuit cancels error caused by switching transistors capacitance. In integrate and hold circuit using JFET switch, gate-to-source capacitance causes error in output voltage. Differential connection cancels out error. Applications in systems where very low voltages sampled or many integrate-and -hold cycles before circuit is reset.
Matlin, M.↗
Techniques for avoiding discrimination errors in the dynamic sampling of condensable vapors
In the mass spectrometric sampling of dynamic systems, measurements of the relative concentrations of condensable and noncondensable vapors can be significantly distorted if some subtle, but important, instrumental factors are overlooked. Even with in situ measurements, the condensables are readily lost to the container walls, and the noncondensables can persist within the vacuum chamber and yield a disproportionately high output signal. Where single pulses of vapor are sampled this source of error is avoided by gating either the mass spectrometer ""on'' or the data acquisition instrumentation ""on'' only during the very brief time-window when the initial vapor cloud emanating directly from the vapor source passes through the ionizer. Instrumentation for these techniques is detailed and its effectiveness is demonstrated by comparing gated and nongated spectra obtained from the pulsed-laser vaporization of several materials.
Lincoln, K. A.↗
Sampling errors in satellite estimates of tropical rain
The GATE rainfall data set is used in a statistical study to estimate the sampling errors that might be expected for the type of snapshot sampling that a low earth-orbiting satellite makes. For averages over the entire 400-km square and for the duration of several weeks, strong evidence is found that sampling errors less than 10 percent can be expected in contributions from each of four rain rate categories which individually account for about one quarter of the total rain.
Mcconnell, Alan↗
New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
hardware description language (HDL)↗
New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
Error Correction and Detection (EDAC)↗
The beam filling error in the Nimbus 5 electronically scanning microwave radiometer observations of Global Atlantic Tropical Experiment rainfall
A comparison of rain rates retrieved from the Nimbus 5 electronically scanning microwave radiometer brightness temperatures and observed from shipboard radars during the Global Atlantic Tropical Experiment (GATE) phase I shows that the beam filling error is the major source of discrepancy between the two. When averaged over a large scene (the GATE radar array, 400 km in diameter), the beam filling error is quite stable, being 50 percent of the observed rain rate. This suggests the simple procedure of multiplying retrieved rain rates by 2 (correction factor). A statistical model of the beam filling error is developed by envisioning an idealized instrument field-of-view that encompasses an entire gamma distribution of rain rates. A modeled correction factor near 2 is found for rain rate and temperature characteristics consistent with GATE conditions. The statistical model also suggests that the correction factor varies from 1.5 to 2.5 for suppressed to enhanced tropical convective regimes, and decreases to 1.5 as the freezing level and average depth of the rain column decreases to 2.5 km.
Short, David A.↗
Identifying Human Factors Issues in Aircraft Maintenance Operations
Maintenance operations incidents submitted to the Aviation Safety Reporting System (ASRS) between 1986-1992 were systematically analyzed in order to identify issues relevant to human factors and crew coordination. This exploratory analysis involved 95 ASRS reports which represented a wide range of maintenance incidents. The reports were coded and analyzed according to the type of error (e.g, wrong part, procedural error, non-procedural error), contributing factors (e.g., individual, within-team, cross-team, procedure, tools), result of the error (e.g., aircraft damage or not) as well as the operational impact (e.g., aircraft flown to destination, air return, delay at gate). The main findings indicate that procedural errors were most common (48.4%) and that individual and team actions contributed to the errors in more than 50% of the cases. As for operational results, most errors were either corrected after landing at the destination (51.6%) or required the flight crew to stop enroute (29.5%). Interactions among these variables are also discussed. This analysis is a first step toward developing a taxonomy of crew coordination problems in maintenance. By understanding what variables are important and how they are interrelated, we may develop intervention strategies that are better tailored to the human factor issues involved.
Veinott, Elizabeth S.↗
GEOS-C altimeter attitude bias error correction
A pulse-limited split-gate-tracking radar altimeter was flown on Skylab and will be used aboard GEOS-C. If such an altimeter were to employ a hypothetical isotropic antenna, the altimeter output would be independent of spacecraft orientation. To reduce power requirements the gain of the altimeter antenna proposed is increased to the point where its beamwidth is only a few degrees. The gain of the antenna consequently varies somewhat over the pulse-limited illuminated region of the ocean below the altimeter, and the altimeter output varies with antenna orientation. The error introduced into the altimeter data is modeled empirically, but close agreements with the expected errors was not realized. The attitude error effects expected with the GEOS-C altimeter are modelled using a form suggested by an analytical derivation. The treatment is restricted to the case of a relatively smooth sea, where the height of the ocean waves are small relative to the spatial length (pulse duration times speed of light) of the transmitted pulse.
Marini, J. W.↗
Using a Commercial Ethernet PHY Device in a Radiation Environment
This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.
Parks, Jeremy↗