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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0

This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

Shalf, JohnM. [Lawrence Berkeley National Laborato↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
NASA NTRS1990

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Taylor, B.↗
NASA NTRS1976

Implementation of Large Scale Integrated (LSI) circuit design software

Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology.

Kuehlthau, R. L.↗
NASA NTRS1993

Microelectronic Chips For Radiation-Dose Tests

Custom-made single-chip complementary metal-oxide semiconductor (CMOS) integrated circuit designed to reveal effects of ionizing radiation on itself and similar integrated circuits. Potential terrestrial use: safety-oriented monitoring of ionizing radiation at nuclear powerplants, nuclear-waste sites, and the like.

Buehler, Martin G.↗
NASA NTRS1986

GaAs Semi-Insulating Layer for a GaAs Device

Improved design for GaAs electronic device or integrated circuit designed to operate at cryogenic temperatures, customary SiO2 insulating layer replaced by semi-insulating layer of GaAs. Thermal expansions of device and covering layer therefore match closely, and thermal stresses caused by immersion in cryogenic chamber nearly eliminated.

Sherrill, G.↗
NASA NTRS1985

Designing Test Chips for Custom Integrated Circuits

Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

Buehler, M. G.↗
NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗
NASA NTRS1994

Optoelectronic Receiver For Communication And Control

Many operational and diagnostic features integrated into circuit chip. GaAs-based integrated circuit designed to serve as optoelectronic interface in phased-array antenna. Intended function to receive digital control signals transmitted on optical fiber and to convert signals to electronic control signals, which then applied to monolithic microwave integrated circuit (MMIC). Also used in reception of high-rate optical digital communications within computers, between computers, and in signal-distribution systems in aircraft, automobiles, and ships. Interface circuit represents significant improvement over preexisting interface circuits in that its clock-signal-recovery subcircuit requires little or no preamble for immediate synchronization.

Kunath, Richard↗
NASA NTRS1976

High and low threshold P-channel metal oxide semiconductor process and description of microelectronics facility

The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.

Bouldin, D. L.↗
DOE OSTI2025

X-Ray and Particle Detection With the Si(Li) Tracker Module of the GAPS Experiment

Here, this work describes the architecture and the experimental results from the characterization of the lithium-drifted silicon (Si(Li)) detector module, which constitutes the building block of the tracker in the general antiparticle spectrometer (GAPS) experiment to search for dark matter. The instrument is designed for the identification of low-energy cosmic anti-nuclei (antiprotons, antideuterons, and antihelium) to be performed during an Antarctic long-duration balloon flight scheduled for late 2025. The GAPS Si(Li) tracker, that is the core of the instrument, is the assembly of 252 modules, each comprised of four Si(Li) detectors and a full custom-integrated circuit designed for detector readout and produced in a commercial 180-nm planar CMOS technology. A general overview of the detector module architecture and its components is provided, together with a description of the test setup and the experimental results obtained from the characterization of the low-noise analog readout channel. In order to verify the effective operation of the entire module, results concerning the detection of X-rays from a 241Am source and cosmic muons are also provided.

Manghisoni, Massimo [Università di Bergamo (Italy)↗
NASA NTRS2009

In-Phase Power-Combined Frequency Tripler at 300 GHz

This design starts with commercial 85- to 115-GHz sources that are amplified to as much as 250 mW using power amplifiers developed for the Herschel Space Observatory. The frequency is then tripled using a novel waveguide GaAs Schottky diode frequency tripler. This planar diode produces 26 mW at 318 GHz. Peak conversion efficiency is over 15 percent, and the measured bandwidth of about 265 - 30 GHz is limited more by the driving source than by the tripler itself. This innovation is based on an integrated circuit designed originally for a single-chip 260- to 340-GHz balanced tripler. The power-combined version has two mirror-image tripler chips that are power-combined in-phase in a single waveguide block using a compact Y-junction divider at the input waveguide, and a Y-junction combiner at the output waveguide. The tripler uses a split-block waveguide design with two independent DC bias lines.

Maestrini, Alain↗
DOE OSTI2025

Bare Module Testing for the CMS Vertex Detector Upgrade

The High-Luminosity LHC will continue exploring physics beyond the standard model with proton-proton collisions at ten times the luminosity of previous LHC runs. The physics program depends on precise measurements of charged particles near the beams. The CMS experiment will use layers of high-granularity hybrid silicon pixel detectors. Pixelation is achieved by bonding silicon to tiny electrodes, which are directly connected to the specially designed integrated circuit, CROCv2. Pixel detector components are in the pre-production phase, and evaluating prototypes of sensor-chip assemblies from different vendors provides quick feedback and improves reliability during production. This article presents the efforts to test the viability of bare detector assemblies using a manual probe station and electronic charge-injection methods.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1967

Transient sensor development

Pulse width/amplitude- and noise-sensors are updated to integrated circuit design concepts, and rise time/amplitude sensor design is reduced to an operational prototype to make all the sensors compatable for one system operation. Therefore, transients interfering with the design operation of receivers could be individually isolated and identified.

Cash, J.↗