Modeling integrated circuits for computing
Integrated circuit models for computer analysis and design
Herskowitz, G. J.↗
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An eclectic integrated circuit reliability model
A general form of a comprehensive reliability modeling rationale was formulated for the integrated circuit. Integrated device failure models amenable to long term applications were investigated.
Fetcher, B. C.↗
Black-box models for linear integrated circuits
Black box modeling of linear integrated circuits for computer analysis in frequency domain
Murray-Lasso, M. A.↗
Computer-oriented modelling of integrated circuits - Algorithms for the dichotomous presentation of active networks
Computer oriented modeling of integrated circuits - algorithms for dichotomous presentation of active networks
INTEGRATED CIRCUIT↗
MOS integrated circuit fault modeling
Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
Sievers, M.↗
Modeling "Soft" Errors in Bipolar Integrated Circuits
Mathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.
Zoutendyk, J.↗
Characterization and Modeling of 4H-SiC Lateral MOSFETs for Integrated Circuit Design
A new process in 4H-SiC is developed that features n-type buried and inversion channel lateral MOSFETs that are fabricated with several different channel lengths (2-8 mu m) and widths (8-32 mu m) and characterized over a wide temperature range (25 degrees C-225 degrees C). It is shown that the on-resistance of enhancement-mode SiC MOSFETs reduces with temperature despite a reduction in inversion mobility because of the interaction of interface states with temperature. To enable integrated circuit development using the developed MOSFETs, their electrical characteristics are modeled over geometry and temperature using the industry standard PSP MOSFET model. A new mathematical formulation to describe the presence of the interface states is also developed and implemented in the PSP model, and excellent agreement is shown between measurement and simulation using the modified PSP model.
Mudholkar, M↗
An Integrated Magnetic Circuit Model and Finite Element Model Approach to Magnetic Bearing Design
A code for designing magnetic bearings is described. The code generates curves from magnetic circuit equations relating important bearing performance parameters. Bearing parameters selected from the curves by a designer to meet the requirements of a particular application are input directly by the code into a three-dimensional finite element analysis preprocessor. This means that a three-dimensional computer model of the bearing being developed is immediately available for viewing. The finite element model solution can be used to show areas of magnetic saturation and make more accurate predictions of the bearing load capacity, current stiffness, position stiffness, and inductance than the magnetic circuit equations did at the start of the design process. In summary, the code combines one-dimensional and three-dimensional modeling methods for designing magnetic bearings.
Provenza, Andrew J.↗
Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM
As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
CMOS integrated circuits↗
Adaptation of models for minority-carrier devices to integrated circuits
Adaptation of models for minority carrier devices, and applicability in computer design evaluation studies of integrated circuits
ELECTRONIC EQUIPMENT TESTING↗
Analysis of Irradiance Models for Bifacial PV Modules
We describe and compare two methods for modeling irradiance on the back surface of rack-mounted bifacial PV modules: view factor models and ray-tracing simulations. For each method we formulate one or more models and compare each model with irradiance measurements and short circuit current for a bifacial module mounted a fixed tilt rack with three other similarly sized modules. Our analysis illustrates the computational requirements of the different methods and provides insight into their practical applications. We find a level of consistency among the models which indicates that consistent models may be obtained by parameter calibrations.
14 SOLAR ENERGY↗
Integrative Circuit-Host Modeling of a Genetic Switch in Varying Environments
Synthetic biology is advancing into a new phase where real-world applications are emphasized. There is hence an urgent need for mathematical modeling that can quantitatively describe the behaviors of genetic devices in natural, fluctuating environments. We utilize an integrative circuit-host modeling framework to examine the dynamics of a genetic switch and its host cell in varying environments. For both steady-state and transient cases, we find increasing nutrient reduces the bistability region of the phase space and eventually drives the switch from bistability to monostability. In response, cellular growth and proteome partitioning experience the same transition. Antibiotic perturbations cause the similar circuit and host responses as nutrient variations. However, one difference is the trend of growth rate, which augments with nutrient but declines with antibiotic levels. The framework provides a mechanistic scheme to account for both the dynamic and static characteristics of the circuit-host system upon environmental perturbations, underscoring the intimacy of gene circuits and their hosts and elucidating the complexity of circuit behaviors arising from environmental variations.
59 BASIC BIOLOGICAL SCIENCES↗
Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits
A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.
Burns, J. L.↗
A Comprehensive Cross-Model Framework for Benchmarking the Performance of Quantum Hamiltonian Simulations
Not Available
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Cost optimization in low volume VLSI circuits
The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.
Cook, K. B., Jr.↗
Quantitative Study of the Effect of Non-Uniform Irradiance on Module Performance Combining EL and DLIT Imaging with Circuit Modeling
This paper presents a quantitative study of how the non-uniform irradiance from solar simulators and the often overlooked non-uniformities in modules (e.g. mismatched cell performance in a module, connection of cell strings, bypass diodes) affect the measurement accuracy in Si module power calibrations. By implementing spatial non-uniformity maps of solar simulators and experimental diode parameters of individual cells in a module to our circuit model, it enables a better understanding of the interaction of simulator irradiance non-uniformity with module imperfections in module power measurements. The comparison between simulation and experiment shows that with a nonuniform irradiance of 3%, the P MAX deviations could be as low as ~0.5 % for good-quality Si modules, and ~2% for poor-quality Si modules, confirming the sensitivity of module power calibrations to module properties.
14 SOLAR ENERGY↗
Variable Time-Step Implementation for Rapid Quasi-Static Time-Series (QSTS) Simulations of Distributed PV
Distribution system analysis with high penetrations of distributed PV require quasi-static time-series (QSTS) analysis to model the variability introduced on the distribution system, but current QSTS algorithms are prohibitively burdensome and computationally intensive. This paper proposes a variable timestep algorithm to calculate the critical time periods when QSTS simulations should be solved at higher or lower time-resolution and to backtrack for any critical periods that were missed. This variable time-step solver is a new method of performing timeseries simulations with high accuracy while performing the simulation more than 50 times faster. The scalability of the algorithm is demonstrated using a real utility distribution system model with thousands of buses.
14 SOLAR ENERGY↗
Detection of False Data Injection Attacks in Battery Stacks Using Input Noise-Aware Nonlinear State Estimation and Cumulative Sum Algorithms
Grid-scale battery energy storage systems (BESSs) are vulnerable to false data injection attacks (FDIAs), which could be used to disrupt state of charge (SoC) estimation. Inaccurate SoC estimation has negative impacts on system availability, reliability, safety, and the cost of operation. In this article a combination of a Cumulative Sum (CUSUM) algorithm and an improved input noise-aware extended Kalman filter (INAEKF) is proposed for the detection and identification of FDIAs in the voltage and current sensors of a battery stack. The series-connected stack is represented by equivalent circuit models, the SoC is modeled with a charge reservoir model and the states are estimated using the INAEKF. Further, the root mean squared error of the states’ estimation by the modified INAEKF was found to be superior to the traditional EKF. By employing the INAEKF, this article addresses the research gap that many state estimators make asymmetrical assumptions about the noise corrupting the system. Additionally, the INAEKF estimates the input allowing for the identification of FDIA, which many alternative methods are unable to achieve. The proposed algorithm was able to detect attacks in the voltage and current sensors in 99.16% of test cases, with no false positives. Utilizing the INAEKF compared to the standard EKF allowed for the identification of FDIA in the input of the system in 98.43% of test cases.
25 ENERGY STORAGE↗