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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Advanced packaging technologies such as 3D chip stacking, multichip modules (MCMs), and 3D stacks of MCMs provide opportunities for significant reductions in system mass, volume and power.
This paper summarizes and reports a radiation hardened Spacecraft Integrated Circuit Technology to be flown on board the Cassini spacecraft in 1997 A.D. The Multichip Module has been designed to have an operating life of fifeteen (15) years with appropriate derating guidelines for high reliability.
A technique for improving the optical characteristics at the butted edges of linear-multichip focal-plane imaging arrays is presented. It is shown that the air gap between butted imaging chips causes significant crosstalk. By filling the gap with a material that has an index of refraction more closely matched to that of the substrate, it is possible to reduce the optical crosstalk significantly.
Recent changes within NASA's space exploration program favor the design, implementation, and operation of low cost, lightweight, small and micro spacecraft with multiple launches per year. In order to meet the future needs of these missions with regard to the use of spacecraft microelectronics, NASA's advanced flight computing (AFC) program is currently considering industrial cooperation and advanced packaging architectures. In relation to this, the AFC program is reviewed, considering the design and implementation of NASA's AFC multichip module.
LTCC MCMs (Low Temperature Cofired Ceramic MultiChip Module) for RF and wireless systems often use metal filled via holes to improve isolation between the stripline and microstrip interconnects. In this paper, results from a 3D-FEM electromagnetic characterization of microstrip and stripline interconnects with metal filled via fences for isolation are presented. It is shown that placement of a via hole fence closer than three times the substrate height to the transmission lines increases radiation and coupling. Radiation loss and reflections are increased when a short via fence is used in areas suspected of having high radiation. Also, via posts should not be separated by more than three times the substrate height for low radiation loss, coupling, and suppression of higher order modes in a package.
NASA Goddard Space Flight Center has designed a high-density modular 3-D multichip module (MCM) for future spaceflight use. This MCM features a complete modular structure, i.e., each stack can be removed from the package without damaging the structure. The interconnection to the PCB is through the Column Grid Array (CGA) technology. Because of its high-density nature, large power dissipation from multiple layers of circuitry is anticipated and CVD diamond films are used in the assembly for heat conduction enhancement. Since each stacked layer dissipates certain amount of heat, designing effective heat conduction paths through each stack and balancing the heat dissipation within each stack for optimal thermal performance become a challenging task. To effectively remove the dissipated heat from the package, extensive thermal analysis has been performed with finite element methods. Through these analyses, we are able to improve the thermal design and increase the total wattage of the package for maximum electrical performance. This paper provides details on the design-oriented thermal analysis and performance enhancement. It also addresses issues relating to contact thermal resistance between the diamond film and the metallic heat conduction paths.
A Multichip Module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's new 'cheaper, faster, better' missions.
This package provides space for mounting up to five MMIC chips and has three RF and five DC feed-throughs.
Thermal insulation technique permits low and high power electronic chips to operate in the same package without thermal cross-coupling. An alumina glass shield thermally isolates the low power chip from the high power chip while Kovar substrate acts as a heat sink to remove heat from the high power chip.
This paper summarizes and reports a radiation hardened Spacecraft Integrated Sensor/Circut Technology that has been delivered for flight applications to be flown on board STRV-2 (Space Technology Research Vehicle-2).
A compound imager consists of two or more individual chips, each with at least one line array of sensors thereupon. Each chip has a glass support plate attached to the side from which light reaches the line arrays. The chips are butted together end-to-end to make large line arrays of sensors. Because of imperfections in cutting, the butted surfaces define a gap. Light entering in the region of the gap is either lost or falls on an individual imager other than the one for which it is intended. This results in vignetting and/or crosstalk near the butted region. The gap is filled with an epoxy resin or other similar material which, when hardened, has an index of referaction near that of the glass support plate.
Various stripline structures and flip chip interconnect designs for high-speed digital communication systems implemented in low temperature co-fired ceramic (LTCC) substrates are studied in this paper. Specifically, two different transition designs from edge launch 2.4 millimeter connectors to stripline transmission lines embedded in LTCC are discussed. After characterizing the DuPont (sup trademark) 9K7 green tape, different designs are proposed to improve signal integrity for high-speed digital data. The full-wave simulations and experimental data validate the presented designs over a broad frequency band from Direct Current to 50 gigahertz and beyond.
A device has been developed for coherent detection of the polarization of the cosmic microwave background (CMB). A two-stage amplifier has been designed that covers 75-110 GHz. The device uses the emerging 35-nm InP HEMT technology recently developed at Northrop Grumman Corporation primarily for use at higher frequencies. The amplifier has more than 18 dB gain and less than 35 K noise figure across the band. These devices have noise less than 30 K at 100 GHz. The development started with design activities at JPL, as well as characterization of multichip modules using existing InP. Following processing, a test campaign was carried out using single-chip modules at 100 GHz. Successful development of the chips will lead to development of multichip modules, with simultaneous Q and U Stokes parameter detection. This MMIC (monolithic microwave integrated circuit) amplifier takes advantage of performance improvements intended for higher frequencies, but in this innovation are applied at 90 GHz. The large amount of available gain ultimately leads to lower possible noise performance at 90 GHz.
This paper describes a working flight computer Multichip Module developed jointly by JPL and TRW under their respective research programs in a collaborative fashion. The MCM is fabricated by nCHIP and is packaged within a 2 by 4 inch Al package from Coors. This flight computer module is one of three modules under development by NASA's Advanced Flight Computer (AFC) program. Further development of the Mass Memory and the programmable I/O MCM modules will follow. The three building block modules will then be stacked into a 3D MCM configuration. The mass and volume of the flight computer MCM achieved at 89 grams and 1.5 cubic inches respectively, represent a major enabling technology for future deep space as well as commercial remote sensing applications.
To meet new design objectives for drastic reductions in mass, size, and power consumption, the Flight Computer Development Group at JPL is participating in a design study and development of a light-weight, small-sized, low-power 3-D Space Flight Computer. In this paper, we will present a detailed design and tradeoff study of the proposed computer. We will also discuss a complete design of the multichip modules and their size, weight, and power consumption. Prelimimary thermal models will also be discussed.
The intent of this presentation is to give a brief look into the future of electronic packaging for microspacecraft applications. Advancements in electronic packaging technology areas have developed to the point where a system engineer's visions, concepts, and requirements for a microspacecraft can now be a reality. These new developments are ideal candidates for microspacecraft applications. These technologies are capable of bringing about major changes in how we design future spacecraft while taking advantage of the benefits due to size, weight, power, performance, reliability , and cost. This presentation will also cover some advantages and limitations of surface mount technology (SMT), multichip modules (MCM), and wafer scale integration (WSI), and what is needed to implement these technologies into microspacecraft.
Multichip hybrid fabrication techniques for prototype function generator circuits
The technologies of low power TTL and beam lead processing were merged into a single product family. This family offers the power and thermal advantages of low power(54L), while providing the additional reliability advantages of beam leads. The reduction in the power and heat levels also allows the system designer to take advantage, through beam lead, multichip assemblies, of increased package density to reduce system size and weight.