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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

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NASA NTRS1978

Indium antimonide infrared CCD linear imaging arrays with on-chip preprocessing

A description is presented of the fabrication of a new InSb CCD chip based on an improved process which eliminates the limitations inherent with the earlier techniques. This process includes planar junction formation and an aluminum and SiO2 material system which is amenable to state-of-the-art chemical and plasma delineation techniques. Further, the new chip integrates for the first time in monolithic format InSb IR detectors with an InSb CCD. The reported experiments represent the first operation of an InSb infrared CCD array. In addition to fuller characterization of the 20-element charge-coupled infrared imaging device, several factors which influence device performance are currently being addressed. These include surface state density, the CCD output circuit, and storage time (dark current).

Thom, R. D.↗

NASA NTRS1982

Differential imaging using charge-coupled device (CCD) imagers with on-chip charge storage

A CCD technique is described which allows long integration periods between readouts together with moderate chopping rates. During each phase of a differential chopping cycle, one set of charge images is shifted to the center of the chip, which is light sensitive. At the same time, the other set of charge images is shifted under one of two masked areas which serve as charge-storage sites. Since the vertical shifting between phases can be accomplished in much less time than the typical exposure per phase, there is negligible image smearing. For a given light level and chopping rate the performance of this technique is limited primarily by the readout noise and the vertical charge transfer inefficiency. If many transfer cycles are required between readouts, the charge transfer inefficiency will diffuse the accumulated charge images along the vertical columns. Laboratory and astronomical data obtained with this technique using a CCD camera and the 2.3 m telescope on Kitt Peak are presented.

Stockman, H. S.↗

NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗

NASA NTRS1983

Monolithic lead salt-silicon focal plane development

This paper is a summary of work done in the development of monolithic lead salt-silicon infrared focal plane technology. The photoconductive detector materials, PbS and PbSe are chemically deposited onto premetallized silicon MOSFET integrated circuit wafers. A variety of structures based on an implanted PMOS process were fabricated and evaluated. Operational results of an eight-element PbS array multiplexed on-chip are presented along with radiometric measurements on other integrated PbS-silicon MOSFET structures. PbS imagery is shown using one element of a 20-element array integrated on-chip.

Barrett, J. R.↗

NASA NTRS1974

Yield analysis of large capacity magnetic bubble circuits with redundancy design

The fabrication yield of an on-chip modifiable redundant circuit design for a 100M bit serial shift register is evaluated. The yield model is a redundancy design in which there is a primary loop and a set of secondary loops which can be enabled/disabled without introducing blanks to the data stream. This function has a finite yield, the loop-modification yield factor, which must be greater than 0.9 to make the system more economical than the simple nonredundant design. It is further established that small loop capacities greatly degrade the yield because of the effect of the modification yield factor, while large loop capacities degrade the yield because of defects in the operating area. As the modification yield increases the optimum loop capacity decreases. An optimum value for the number of redundant loops exists for each loop capacity. Other factors that affect the yield are the garnet film and the processed circuit.

Bailey, R. F.↗

NASA NTRS1975

A 190 by 244 charge-coupled area image sensor with interline transfer organization

A 190 x 244 element charge coupled area image sensor has been designed, fabricated and tested. This sensor employs an interline transfer organization and buried n-channel technology. It features a novel on-chip charge integrator and a distributed floating gate amplifier for high and low light level applications. The X-Y element count has been chosen to establish the capability of producing an NTSC compatible video signal. The array size is also compatible with the Super 8 lens format. The first few sample devices have been successfully operated at full video bandwidth for both high and low light levels with the charge amplifier system.

Walsh, L. R.↗

NASA NTRS1975

Self-scanned Digicon - A digital image tube for astronomical spectroscopy

We have successfully fabricated, tested, and operated a digital image tube consisting of a magnetically focused image intensifier tube in which a self-scanned linear array of 1024 silicon photodiodes operating in the EBS mode serves as the photoelectron image detector, amplifier, and intermediate image storage device. Integral on-chip MOS shift registers driven by an external clock sequentially interrogate the photodiodes through MOS FET multiplex switch arrays. Each output frame is a sequence of 256 analog pulses on each of four video lines. Laboratory and observing tests show that the output signal is photoelectron shot noise limited over at least a range of 1-100,000 detected photoelectrons per picture element, indicating that single photon detection is achieved. High-resolution astronomical spectroscopy has been carried out in the coude spectrograph of the 2.7-m telescope at McDonald Observatory. Examples are shown.

Tull, R. G.↗

NASA NTRS1976

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Besser, P. J.↗

NASA NTRS1976

Design automation for complex CMOS/SOS LSI hybrid substrates

A design automated approach used to develop thick-film hybrid packages is described. The hybrid packages produced combine thick-film and silicon on sapphire (SOS) laser surface interaction technologies to bring the on-chip performance level of SOS to the subsystem level. Packing densities are improved by a factor of eight over ceramic dual in-line packing; interchip wiring capacitance is low. Due to significant time savings, the design automated approach presented can be expected to yield a 3:1 reduction in cost over the use of manual methods for the initial design of a hybrid.

Ramondetta, P. W.↗

NASA NTRS1978

Integrated detector array preprocessing for infrared astronomical applications

On-board preprocessing of astronomical data from integrated infrared detector arrays and discrete detectors will allow increases in sensitivity and reductions in costs for observations from cryogenic space telescopes. A variety of preprocessing functions for this application, which could be implemented either through analog on-chip devices or through external microprocessors, is identified. Software simulations and laboratory evaluations are underway to determine the effectiveness of these preprocessing schemes.

Mccreight, C. R.↗

NASA NTRS1981

Texas Instruments /TI/ 800 x 800 charge-coupled device /CCD/ image sensor

Very-large area high-performance CCD image sensors with 800 x 800 pixel format have been successfully fabricated and operated on the basis of a three-level polysilicon gate technology. They are thinned to 8 microns over the entire 12.2 x 12.2 mm active area, and are used in the rear illumination mode. The light transfer characteristic has a gamma value of 1.000 + or - 0.002 over most of the dynamic range. Analysis of the noise behavior shows that the device SNR is shot-noise-limited over most of the dynamic range. Simple on-chip signal processing can be performed using an integration well to noiselessly collect signal charge from multiple pixels prior to reading out the charge. A UV-sensitive phosphor has been applied to the chip, yielding a device capable of imaging at wavelengths from the vacuum UV to the near IR.

Blouke, M. M.↗

NASA NTRS1982

Off-line, built-in test techniques for VLSI circuits

It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.

Buehler, M. G.↗

NASA NTRS1982

Charge-coupled device (CCD) television camera for NASA's Galileo mission to Jupiter

The CCD detector under construction for use in the slow-scan television camera for the NASA Galileo Jupiter orbiter to be launched in 1985 is presented. The science objectives and the design constraints imposed by the earth telemetry link, platform residual motion, and the Jovian radiation environment are discussed. Camera optics are inherited from Voyager; filter wavelengths are chosen to enable discrimination of Galilean-satellite surface chemical composition. The CCO design, an 800 by 800-element 'virtual-phase' solid-state silicon image-sensor array with supporting electronics, is described with detailed discussion of the thermally generated dark current, quantum efficiency, signal-to-noise ratio, and resolution. Tests of the effect of ionizing radiation were performed and are analyzed statistically. An imaging mode using a 2-1/3-sec frame time and on-chip summation of the signal in 2 x 2 blocks of adjacent pixels is designed to limit the effects of the most extreme Jovian radiation. Smearing due to spacecraft/target relative velocity and platform instability will be corrected for via an algorithm maximizing spacial resolution at a given signal-to-noise level. The camera is expected to produce 40,000 images of Jupiter and its satellites during the 20-month mission.

Klaasen, K. P.↗

NASA NTRS1984

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Long, S. I.↗

NASA NTRS1985

Shortwave infrared 512 x 2 line sensor for earth resources applications

As part of the NASA remote-sensing Multispectral Linear Array Program, an edge-buttable 512 x 2 IRCCD line image sensor with 30-micron Pd2Si Schottky-barrier detectors is developed for operation with passive cooling at 120 K in the 1.1-2.5 micron short infrared band. On-chip CCD multiplexers provide one video output for each 512 detector band. The monolithic silicon line imager performance at a 4-ms optical integration time includes a signal-to-noise ratio of 241 for irradiance of 7.2 microwatts/sq cm at 1.65 microns wavelength, a 5000 dynamic range, a modulation transfer function, greater than 60 percent at the Nyquist frequency, and an 18-milliwatt imager chip total power dissipation. Blemish-free images with three percent nonuniformity under illumination and nonlinearity of 1.25 percent are obtained. A five SWIR imager hybrid focal plane was constructed, demonstrating the feasibility of arrays with only a two-detector loss at each joint.

Tower, J. R.↗

NASA NTRS1987

Command/response protocols and concurrent software

A version of the program to control the parallel jaw gripper is documented. The parallel jaw end-effector hardware and the Intel 8031 processor that is used to control the end-effector are briefly described. A general overview of the controller program is given and a complete description of the program's structure and design are contained. There are three appendices: a memory map of the on-chip RAM, a cross-reference listing of the self-scheduling routines, and a summary of the top-level and monitor commands.

Bynum, W. L.↗

NASA NTRS1985

Large area CCD image sensors for scientific applications

The designs of the 512 x 512 pixel and 2048 x 2048 pixel CCD sensors developed for scientific imaging are described. Both sensors are manufactured using the three phase, three level polysilicon gate technology, and the architecture of the chips is series-parallel-series. The components of the two different on-chip amplifiers are examined. The sensors are thinned and operated in the back side illumination mode to ensure the highest quantum efficiency. The performances of a number of front side illuminated devices and two thinned rear illuminated chips are evaluated. It is observed that the sensors equal or exceed their proposed charge transfer efficiency of 0.99999, the noise level of 2 e- and 20 e- at 50 kp/s, the quantum efficiency of 40 percent at 400 microns and 70 percent at 700 microns, and of the well capacity of greater than 500 ke-/pixel.

Blouke, M. M.↗

NASA NTRS1986

Holographic optical interconnects for VLSI

This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementation s of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design techniques and, finally, presents some preliminary measurements on various system components.

Bergman, L. A.↗