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Results for “p-type transistor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Transport Modeling for Metallic Electrode: Semiconducting Nanotube Systems

Recently, current-voltage (I-V) characteristics have been reported by Collins et al. for a system with a scanning tunneling microscope (STM) tip and a carbon nanotube. The STM tip was driven forward into a film of many entangled nanotubes on a substrate, and then was retracted, so that one of nanotubes bridged the STM and the film. I-V characteristics had two different patterns for different heights. One showed large dI/ dV with V greater than 0, small dI/dV with V less than 0, and I = 0 near V = 0 (type-I), while the other showed rectification, i.e., I does not equal 0 only with V less than 0 (type-II), with the tip grounded. We propose a physical mechanism to explain the observed I-V patterns. We consider that the observed characteristics strongly reflected the nature of the tip (metal) - nanotube (semiconductor) contact. The other end of the nanotube was entangled well in the film, and simply provided a good Ohmic contact. We will argue that there are two different contact modes: vacuum gap and touching modes, depending on the presence or absence of a tiny vacuum gap d approx. 0.1 - 0.2 nm at the junction. These modes may be related to physisorption and chemisorption, respectively. Once admitting their existence, it is naturally shown that I-V characteristics are type-I in the vacuum gap mode, and type-II in the touching mode. We argue that the nanotube had to be an n-type semiconductor judging from the I-V characteristics, contrary to often observed p-type in the transistor applications, where p-type is probably due to the oxidation in air or the trapped charges in the silicon dioxide. Additional information is contained in the original extended abstract.

Yamada, Toshishige↗
NASA NTRS1993

Characterization of Si (sub X)Ge (sub 1-x)/Si Heterostructures for Device Applications Using Spectroscopic Ellipsometry

Spectroscopic ellipsometry (SE) characterization of several complex Si (sub X)Ge (sub 1-x)/Si heterostructures prepared for device fabrication, including structures for heterojunction bipolar transistors (HBT), p-type and n-type heterostructure modulation doped field effect transistors, has been performed. We have shown that SE can simultaneously determine all active layer thicknesses, Si (sub X)Ge (sub 1-x) compositions, and the oxide overlayer thickness, with only a general knowledge of the structure topology needed a priori. The characterization of HBT material included the SE analysis of a Si (sub X)Ge (sub 1-x) layer deeply buried (600 nanometers) under the silicon emitter and cap layers. In the SE analysis of n-type heterostructures, we examined for the first time a silicon layer under tensile strain. We found that an excellent fit can be obtained using optical constants of unstrained silicon to represent the strained silicon conduction layer. We also used SE to measure lateral sample homogeneity, providing quantitative identification of the inhomogeneous layer. Surface overlayers resulting from prior sample processing were also detected and measured quantitatively. These results should allow SE to be used extensively as a non-destructive means of characterizing Si (sub X)Ge (sub 1-x)/Si heterostructures prior to device fabrication and testing.

Sieg, R. M.↗
NASA NTRS1985

Heavily doped polysilicon-contact solar cells

The first use of a (silicon)/heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact (BOC) control samples, the polysilicon-back solar cells show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Lindholm, F. A.↗
NASA NTRS1985

Front and back polysilicon-contacted silicon solar cells

The first use of a (silicon)/ (heavily doped polysilicon)/ (metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact control samples, the polysilicon-back solar cells show improvements in red spectral response and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Lindholm, F. A.↗
NASA NTRS1964

Economical fabrication process produces high quality junction transistors

A convenient, three-step fabrication process, with a p-type layer of gallium arsenide vapor deposited on a starting wafer of germanium, is used to produce heterojunction-homojunction p-n-p transistors. These are of high quality with good injection efficiency and low capacitance.

Source record↗
NASA NTRS1986

Fabrication of an X-Ray Imaging Detector

X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.

Alcorn, G. E.↗
NASA NTRS1988

Carbon doping in molecular beam epitaxy of GaAs from a heated graphite filament

Carbon doping of GaAs grown by molecular beam epitaxy has been obtained for the first time by use of a heated graphite filament. Controlled carbon acceptor concentrations over the range of 10 to the 17th-10 to the 20th/cu cm were achieved by resistively heating a graphite filament with a direct current power supply. Capacitance-voltage, p/n junction and secondary-ion mass spectrometry measurements indicate that there is negligible diffusion of carbon during growth and with postgrowth rapid thermal annealing. Carbon was used for p-type doping in the base of Npn AlGaAs/GaAs heterojunction bipolar transistors. Current gains greater than 100 and near-ideal emitter heterojunctions were obtained in transistors with a carbon base doping of 1 x 10 to the 19th/cu cm. These preliminary results indicate that carbon doping from a solid graphite source may be an attractive substitute for beryllium, which is known to have a relatively high diffusion coefficient in GaAs.

Malik, R. J.↗
NASA NTRS1979

Semiconductor technology program. Progress briefs

The current status of NBS work on measurement technology for semiconductor materials, process control, and devices is reported. Results of both in-house and contract research are covered. Highlighted activities include modeling of diffusion processes, analysis of model spreading resistance data, and studies of resonance ionization spectroscopy, resistivity-dopant density relationships in p-type silicon, deep level measurements, photoresist sensitometry, random fault measurements, power MOSFET thermal characteristics, power transistor switching characteristics, and gross leak testing. New and selected on-going projects are described. Compilations of recent publications and publications in press are included.

Bullis, W. M.↗
NASA NTRS1981

A gallium phosphide high-temperature bipolar junction transistor

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

Zipperian, T. E.↗
NASA NTRS1982

Space solar cell technology development - A perspective

The developmental history of photovoltaics is examined as a basis for predicting further advances to the year 2000. Transistor technology was the precursor of solar cell development. Terrestrial cells were modified for space through changes in geometry and size, as well as the use of Ag-Ti contacts and manufacture of a p-type base. The violet cell was produced for Comsat, and involved shallow junctions, new contacts, and an enhanced antireflection coating for better radiation tolerance. The driving force was the desire by private companies to reduce cost and weight for commercial satellite power supplies. Liquid phase epitaxial (LPE) GaAs cells are the latest advancement, having a 4 sq cm area and increased efficiency. GaAs cells are expected to be flight ready in the 1980s. Testing is still necessary to verify production techniques and the resistance to electron and photon damage. Research will continue in CVD cell technology, new panel technology, and ultrathin Si cells.

Scott-Monck, J.↗
NASA NTRS2004

Design of an Auto-zeroed, Differential, Organic Thin-film Field-effect Transistor Amplifier for Sensor Applications

Organic strain gauge and other sensors require high-gain, precision dc amplification to process their low-level output signals. Ideally, amplifiers would be fabricated using organic thin-film field-effect transistors (OTFT's) adjacent to the sensors. However, OTFT amplifiers exhibit low gain and high input-referred dc offsets that must be effectively managed. This paper presents a four-stage, cascaded differential OTFT amplifier utilizing switched capacitor auto-zeroing. Each stage provides a nominal voltage gain of four through a differential pair driving low-impedance active loads, which provide common-mode output voltage control. p-type pentacence OTFT's are used for the amplifier devices and auto-zero switches. Simulations indicate the amplifier provides a nominal voltage gain of 280 V/V and effectively amplifies a 1-mV dc signal in the presence of 500-mV amplifier input-referred dc offset voltages. Future work could include the addition of digital gain calibration and offset correction of residual offsets associated with charge injection imbalance in the differential circuits.

large-area electronics↗
NASA NTRS2003

Long-Term Reliability of High Speed SiGe/Si Heterojunction Bipolar Transistors

Accelerated lifetime tests were performed on double-mesa structure Si/Si0.7Ge0.3/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175C-275C. Both single- and multiple finger transistors were tested. The single-finger transistors (with 5x20 micron sq m emitter area) have DC current gains approximately 40-50 and f(sub T) and f(sub MAX) of up to 22 GHz and 25 GHz, respectively. The multiple finger transistors (1.4 micron finger width, 9 emitter fingers with total emitter area of 403 micron sq m) have similar DC current gain but f(sub T) of 50 GHz. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REID has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of the devices at room temperature is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation. SiGe/Si based amplifier circuits were also subjected to lifetime testing and we extrapolate MTTF is approximately 1.1_10(exp 6) hours at 125iC junction temperature from the circuit lifetime data.

Ponchak, George E.↗
NASA NTRS2001

Long-Term Reliability of SiGe/Si HBTs From Accelerated Lifetime Testing

Accelerated lifetime tests were performed on double-mesa structure Si(0.7)Ge(0.3)/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175 C-275 C. The transistors (with 5x20 sq micron emitter area) have DC current gains approx. 40-50 and f(sub T) and f(sub max) of up to 22 GHz and 25 GHz, respectively. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REED has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of these devices at room temperature under 1.35 x 10(exp 4) A/sq cm current density operation is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation.

Bhattacharya, Pallab↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS1999

Copper-Based OHMIC Contracts for the Si/SiGe Heterojunction Bipolar Transistor Structure

Silicon based heterojunction bipolar transistors (HBT) with SiGe base are potentially important devices for high-speed and high-frequency microelectronics. These devices are particularly attractive as they can be fabricated using standard Si processing technology. However, in order to realize the full potential of devices fabricated in this material system, it is essential to be able to form low resistance ohmic contacts using low thermal budget process steps and have full compatibility with VLSI/ULSI processing. Therefore, a study was conducted in order to better understand the contact formation and to develop optimized low resistance contacts to layers with doping densities corresponding to the p-type SiGe base and n-type Si emitter regions of the HBTS. These as-grown doped layers were implanted with BF(sub 2) up to 1 X 10(exp 16)/CM(exp 2) and As up to 5 x 10(exp 15)/CM2, both at 30 keV for the p-type SiGe base and n-type Si emitter layers, respectively, in order to produce a low sheet resistance surface layer. Standard transfer length method (TLM) contact pads on both p and n type layers were deposited using an e-beam evaporated trilayer structure of Ti/CufTi/Al (25)A/1500A/250A/1000A). The TLM pads were delineated by a photoresist lift-off procedure. These contacts in the as-deposited state were ohmic, with specific contact resistances for the highest implant doses of the order of 10(exp -7) ohm-CM2 and lower.

Das, Kalyan↗
NASA NTRS1974

GaAs transistors formed by Be or Mg ion implantation

N-p-n transistor structures have been formed in GaAs by implanting n-type substrates with Be ions to form base regions and then implanting them with 20-keV Si ions to form emitters. P-type layers have been produced in GaAs by implantation of either Mg or Be ions, with substrate at room temperature, followed by annealing at higher temperatures.

Hunsperger, R. G.↗
NASA NTRS1987

Floating emitter solar cell

A front surface contact floating emitter solar cell transistor is provided in a semiconductor body (n-type), in which floating emitter sections (p-type) are diffused or implanted in the front surface. Between the emitter sections, a further section is diffused or implanted in the front surface, but isolated from the floating emitter sections, for use either as a base contact to the n-type semiconductor body, in which case the section is doped n+, or as a collector for the adjacent emitter sections.

Chih, Sah↗
NASA NTRS2000

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

Kuczmarski, Maria A.↗