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Phase-locked-loop phase modulator has the capability of generating a 6.8MHz carrier at modulation indexes as high as 2.5, with a distortion of the demodulated signal of less than 5 percent. These characteristics are obtained without the use of multipliers.
A phase locked loop utilizing digital techniques to control the closed loop bandwidth of the RF carrier phase locked loop in a receiver provides high sensitivity and a wide dynamic range for signal reception. After analog to digital conversion, a digital phase locked loop bandwidth controller provides phase error detection with automatic RF carrier closed loop tracking bandwidth control to accommodate several modes of transmission.
Phase-locked or APC loops have found increasing applications in recent years as tracking filters, synchronizing devices, and narrowband FM discriminators. Considerable work has been performed to determine the noise-squelching properties of the loop when it is operating in or near phase lock and is functioning as a linear coherent detector. However, insufficient consideration has been devoted to the non-linear behavior of the loop when it is out of lock and in the process of pulling in. Experimental evidence has indicated that there is a strong tendency for phase-locked loops to achieve lock under most circumstances. However, the analysis which has appeared in the literature iis limited to the acquisition of a constant frequency reference signal with only one phase-locked loop filter configuration. This work represents an investigation of frequency acquisition properties of phase-locked loops for a variety of reference-signal behavior and loop configurations
Phase-lock loop demodulator ability to acquire and remain locked on signal under noise and pulse interference
Hybrid phase lock loop model derived by Fokker-Planck technique
Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate.
Advanced design for digital phase-lock loop (DPLL) allows loop gains higher than those used in other designs. Divided into two major components: counterrotation processor and tracking processor. Notable features include use of both phase and rate-of-change-of-phase feedback instead of frequency feedback alone, normalized sine phase extractor, improved method for extracting measured phase, and improved method for "compressing" output rate.
Phase acquisition times of type II and III loops typical of the Advanced Receiver are studied by computer simulations when the loops are disturbed by gaussian noise. Reliable estimates are obtained by running 5000 trials for each combination of loop signal-to-noise ratio (SNR) and frequency offset. The probabilities of acquisition are shown versus time from start of acquisition for various loop SNRs and frequency offsets. For frequency offsets smaller than one-fourth of the loop bandwidth and for loop SNRs of 10 dB and higher, the loops acquire with probability 0.99 within 2.5 B sub L for type II loops and within 7/B sub L for type III loops.
The phase model for the generalized multifilter phase-lock loop (M PLL) is considered and state equations for this model are derived. A linear analysis is presented to aid in the preliminary design of an M PLL and to indicate the noise improvement over a conventional phase-lock loop (PLL). Performance characteristics are examined for an M PLL with low-pass and bandpass characteristics used in a specific FM communication system. Both single and double sinusoidal FM are used and a region of proper operation of the M PLL is determined in terms of modulation index and modulati ng frequency. These results are obtained from both analog and digital computer simulation of the nonlinear system.
Digital communication hybrid phase locked loop nonlinear feedback system with modulation and carrier components enhancing phase estimation
Stationary phase error variance for second order phase locked loop for low signal to noise ratios
The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!
Improved phase locked loop receiver tracks and demodulates a signal whose signal-to-noise ratio may be low and whose information sidebands are close in frequency. This receiver recovers the carrier from input signals and applies it to a demodulator which recovers the sidebands.
Phase locked loop damping characteristics optimization based on input rms error rate minimization and transient error integral square value limitation
An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.
A phase modulated wave that may have no carrier power is demodulated by a phase locked loop including a phase detector for deriving an A.C. data output signal having a magnitude and a phase indicative of the phase of the modulated wave. A feedback loop responsive to the data output signal restores power to the carrier frequency component to the loop. In one embodiment, the feedback loop includes a phase modulator responsive to the phase modulated wave and the data output signal. In a second embodiment, carrier frequency power is restored by differentiating the data output signal and supplying the differentiated signal to an input of a voltage controlled oscillator included in the phase locked loop.
A double reference pulse phase locked loop is described which measures the phase shift between tone burst signals initially derived from the same periodic signal source (voltage controlled oscillator) and delayed by different amounts because of two different paths. A first path is from the transducer to the surface of a sample and back. A second path is from the transducer to the opposite surface and back. A first pulse phase locked loop including a phase detector and a phase shifter forces the tone burst signal delayed by the second path in phase quadrature with the periodic signal source. A second pulse phase locked loop including a second phase detector forces the tone burst signals delayed by the first path into phase quadrature with the phase shifted periodic signal source.
Nonlinear behavior of phase-locked loops with rapidly varying phase error is examined by using computer phase-plane analysis. The phase variation is modeled by a sinusoidal function. Threshold loop parameters are presented for both sinusoidal and sawtooth phase comparators.