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Results for “semiconductor device manufacture”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Conductive strip based mask for metallization of semiconductor devices

Methods of manufacturing a semiconductor device, and resulting semiconductor device are described. In an example, the method for manufacturing a semiconductor device include forming a semiconductor region and forming a metal seed region over the semiconductor region. The method can include placing a conductive strip over a first portion of the metal region, where the conductive strip is formed over the semiconductor region. The method can include bonding a contacting portion of the conductive strip to the first portion the metal region. The method can include etching a second portion of the metal region and where the conductive strip inhibits etching of the first portion of the metal region. In an example, the conductive strip can have a coating. In one example, the semiconductor device can be a solar cell.

14 SOLAR ENERGY↗
NASA NTRS1993

Method for anisotropic etching in the manufacture of semiconductor devices

Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by hyperthermal atomic oxygen beams (translational energies of 0.2 to 20 eV, preferably 1 to 10 eV). Etching with hyperthermal oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask protected areas.

Koontz, Steven L.↗
DOE OSTI2024

Science challenges and research opportunities for plasma applications in microelectronics

Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Machine Learning of Plasma Science for Next Generation Microelectronics (Project Final Report)

Low temperature plasmas (LTPs) are an enabling technology behind reducing device dimensions and the continuation of Moore’s Law. It is estimated that 40-45% of all process steps necessary to manufacture semiconductor devices involve LTPs. However, challenges in plasma process design and continuous incorporation of novel materials for new device architectures are pushing the limits of what is possible with current plasma technology. For example, creating higher aspect ratio structures and etching features at the atomic scale both require finer control of the ion energy/velocity at wafer surfaces. To support these types of future innovations in the plasma processing systems that Sandia and the DOE rely upon, we have developed novel diagnostics, simulations, and machine learning capabilities to discover, characterize, and predict plasma phenomena affecting the ion energy/velocity distribution function (IEDF). These efforts also supported research program development and external collaboration with industry and academia through Sandia’s Plasma Research Facility (PRF). This report will focus on the following topics and accomplishments of this three year LDRD project, briefly summarized.

42 ENGINEERING↗
DOE OSTI2024

Transformer coupled toroidal wave-heated remote plasma sources operating in Ar/NF 3 mixtures

Remote plasmas are used in semiconductor device manufacturing as sources of radicals for chamber cleaning and isotropic etching. In these applications, large fluxes of neutral radicals (e.g. F, O, Cl, H) are desired with there being negligible fluxes of potentially damaging ions and photons. One remote plasma source (RPS) design employs toroidal, transformer coupling using ferrite cores to dissociate high flows of moderately high pressure (up to several Torr) electronegative gases. In this paper, results are discussed from a computational investigation of moderate pressure, toroidal transformer coupled RPS sustained in Ar and Ar/NF 3 mixtures. Operation of the RPS in 1 Torr (133 Pa) of argon with a power of 1.0 kW at 0.5 MHz and a single core produces a continuous toroidal plasma loop with current continuity being maintained dominantly by conduction current. Operation with dual cores introduces azimuthal asymmetries with local maxima in plasma density. Current continuity is maintained by a mix of conduction and displacement current. Operation in NF 3 for the same conditions produces essentially complete NF 3 dissociation. Electron depletion as a result of dissociative attachment of NF 3 and NF x fragments significantly alters the discharge topology, confining the electron density to the downstream portion of the source where the NFx density has been lowered by this dissociation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Lithography-Free Mesa Isolation of III–V Solar Cells Through Laser Ablation

Eliminating photolithography from solar cell processing is a significant opportunity for cost reduction for III-V solar cells. Here, in this work, we explore femtosecond laser ablation as an alternative to contact photolithography and wet chemical etching for mesa isolation. We demonstrate both GaAs and GaInP solar cells mesa-isolated by femtosecond laser ablation with minimal to no loss in solar cell performance. We show the best results with a 400 fs UV pulsed laser and a short clean-up etch that also serves as a contact layer removal etch.

14 SOLAR ENERGY↗
NASA NTRS2019

Molten Target Sputtering: Non-Conventional Method for High Mobility Si0.15Ge0.85 Growth at 500°C

Since electrons travel over 100 times faster in Silicon-Germanium (SiGe) than in pure Si due to the low effective masses associated with Ge and SiGe-based devices continue to replace Si-based solid-state electronic devices. SiGe thin film on sapphire was successfully grown at 890°C, using a magnetron sputtering system within heteroepitaxial framework. However, SiGe growth at 890oC is a costly and difficult process to produce as a uniform wafer for semiconductor device manufacturing due to thermal soak times, and geometric thermal shadowing from the wafer holder. To leverage the semiconducting capabilities of SiGe, novel processing techniques for SiGe film growth with decreased thermal loading are required. This paper introduces the Molten Target Sputtering (MTS) method that produces high mobility SiGe on sapphire below 500°C. This non-conventional method has the advantage of high kinetic energy, high-energy latency, and high flux density of sputtered atoms by combining benefits of both magnetron sputtering and thermal evaporation. For the MTS method, a 1~2 mm (depth and width) ring-shaped groove was cut between the center magnet and surrounded by electromagnets creating a circular cavity between the copper plate and source target materials that melt the target material. The SiGe grown from the MTS shows continuous morphology and 99.7% single crystal Si0.15Ge0.85 films. The Hall electron mobilities of the Si0.15Ge0.85 are 456 sq. cmV(exp -1)s(exp -1) and 123.9 sq. cmV(exp -1)s(exp -1) at 5.59 x 10(exp 18) cubic cm and 3.5 x 10(exp 20) cubic cm carrier concentration at 22.38°C, respectively. This is approximately 5.5 times higher than that of Si and similar to the Ge value at equivalent carrier concentrations and temperatures.

High mobility SiGe↗
NASA NTRS1979

Procedure for pressure contact on high-power semiconductor devices free of thermal fatigue

To eliminate thermal fatigue, a procedure for manufacturing semiconductor power devices with pure pressure contact without solid binding was developed. Pressure contact without the use of a solid binding to avoid a limitation of the maximum surface in the contact was examined. A silicon wafer covered with a relatively thick metal layer is imbedded with the aid of a soft silver foil between two identically sized hard contact discs (molybdenum or tungsten) which are rotationally symmetrical. The advantages of this concept are shown for large diameters. The pressure contact was tested successfully in many devices in a large variety of applications.

Knobloch, J.↗
DOE OSTI2026

Lithography-Free Mesa Isolation by Laser Ablation for Multijunction III-V Photovoltaic Space Power Generation

Eliminating photolithography from photovoltaic device processing is a significant opportunity for cost reduction and increased manufacturing throughput. In this work, we test femtosecond laser ablation and scribing as an alternative to contact photolithography and wet chemical etching for mesa isolation of multijunction devices. We demonstrate that upright multijunction devices isolated by using the laser as a scribe to cleave through the substrate had virtually no performance loss when compared to a baseline device processed with photolithography. By contrast, devices isolated by laser ablating through the active layers have performance losses that cannot be fully eliminated with postprocess etching. This demonstration of photolithography-free mesa isolation with no performance losses is promising as a pathway to less expensive and higher throughput III-V device manufacturing.

14 SOLAR ENERGY↗
DOE OSTI2022

The Other Artificial Intelligence Hardware Problem

The consolidation of leading-edge semiconductor manufacturing in one company in one country poses two problems: a short-term strategic risk and a long-term innovation risk. Furthermore, both problems remain underexplored because advances in artificial intelligence (AI) algorithms have compensated for a relative lack of advances in AI hardware.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1989

Calculating Obscuration Ratios Of Contaminated Surfaces

Equations derived to estimate obscuration ratios of surfaces contaminated by particles. Ratio is fraction of surface area covered by particles. Useful as index of cleanliness in clean-room operations in manufacturing of semiconductor devices, magnetic recording media, optical devices, and pharmaceutical and biotechnological products.

Barengoltz, Jack B.↗
NASA NTRS1990

Surface modification using low energy ground state ion beams

A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.

Chutjian, Ara↗
DOE OSTI2024

Evaluation of Converter Performance Considering Static and Dynamic Device Part-to-Part Variability

This paper presents a methodology to incorporate and analyze the impact of semiconductor device part-to-part variation on power converter performance. By integrating extensive static and dynamic device characterization data with an automated compact model generation process that reflects manufacturing variability, device models with inherent variability features are utilized in converter simulations for a comprehensive assessment of performance impacts. The traditional converter performance evaluation process typically yields fixed efficiency values, often dismissing the inherent part-to-part variability caused by the manufacturing process of semiconductor devices. To address this limitation, a large population of devices was characterized to capture variations in static parameters-such as transfer, output, and capacitance characteristics-as well as dynamic behaviors, including switching losses. This data-driven approach enables the development of individual compact models, which were then integrated into converter simulations to evaluate efficiency ranges rather than single point estimated values. The converter simulation results show that part-to-part component variation can lead to significant efficiency deviations, exceeding several percentage points in high-power conversion applications. By offering a more accurate representation of converter behavior under real-world manufacturing conditions, this methodology enables designers to anticipate performance variability, improving the robustness of power converter designs.

device characterization↗
NASA NTRS1997

Etch Profile Simulation Using Level Set Methods

Etching and deposition of materials are critical steps in semiconductor processing for device manufacturing. Both etching and deposition may have isotropic and anisotropic components, due to directional sputtering and redeposition of materials, for example. Previous attempts at modeling profile evolution have used so-called "string theory" to simulate the moving solid-gas interface between the semiconductor and the plasma. One complication of this method is that extensive de-looping schemes are required at the profile corners. We will present a 2D profile evolution simulation using level set theory to model the surface. (1) By embedding the location of the interface in a field variable, the need for de-looping schemes is eliminated and profile corners are more accurately modeled. This level set profile evolution model will calculate both isotropic and anisotropic etch and deposition rates of a substrate in low pressure (10s mTorr) plasmas, considering the incident ion energy angular distribution functions and neutral fluxes. We will present etching profiles of Si substrates in Ar/Cl2 discharges for various incident ion energies and trench geometries.

Hwang, Helen H.↗
DOE OSTI2024

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into “Beyond CMOS” and “More than Moore” paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. Finally, the outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

36 MATERIALS SCIENCE↗
NASA NTRS1971

Use a SEM on a production line

Scanning electron microscope for poor metallization detection in manufacturing cycle of semiconductor devices

Adolphsen, J. W.↗