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At least 19 records

A Computational Efficient Space-Vector Modulation Scheme for A Hybrid Seven-Level Converter for Medium Voltage Grid-Tied Applications

In this paper, a fast space-vector modulation (SVM) scheme is proposed for a hybrid 7-level (7-L) converter, i.e., cascaded T-type converter and H-bridge converters, for grid-tied applications. Using oblique coordinate reference, the proposed SVM can quickly locate the switching triangle enclosing the reference vector in the 7-L space vector diagram. Then all available switching sequences and vector duty cycles are acquired by straightforward calculation without using any look-up tables, which significantly reduces the computational cost. The floating capacitor voltages are also stabilized by using the proposed SVM. Experimental studies on a scale-down prototype are presented in this work to validate the effectiveness of the proposed scheme.

Diao, Fei↗

A Simple Space Vector Modulation of High-Frequency AC Linked Three-Phase-to-Single-Phase/DC Converter

High frequency (HF) ac linked converter functions well to interface between buses with different voltage types. Using a three-phase-to-single-phase matrix converter, a single-phase cyclo converter, and a HF transformer, we can compose a HF ac linked converter to interface between three-phase ac grids and single-phase ac or dc distributed generations (DGs). In this paper, a novel space vector modulation (SVM) method is proposed for such kind of converter. The proposed SVM method converts the mains three-phase ac voltage to a HF ac voltage at the primary side of transformer, and then unfolds the HF ac voltage to a single-phase ac or dc voltage at the secondary side of transformer. Without need to compute separate switching signals for the primary and secondary converters and then coordinate their operations elaborately, the proposed SVM method can be easily implemented by incorporating the HF chopping into the SVM of traditional indirect matrix converter. Therefore, no complicated duty cycle computation or elaborate switching states combination is required. Simulation and hardware-in-loop implementation demonstrate the validity of the proposed method.

42 ENGINEERING↗

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗

Reliability Improvement by Fault-Tolerant Operation of NPC Inverter for Motor Driving

The high-reliability operation of three-level inverters is crucial to prevent equipment damage, process downtime, and economic losses. This article investigates a three-level neutral-point-clamped inverter under all possible combinations of open-circuit and short-circuit faults and proposes a new postfault operation method without adding extra hardware. This method provides comprehensive solution for operations after single and multiple-device failures, increasing the inverter reliability by 24%. This article classified postfault modulations and uncovered previously unknown fault scenarios that can be addressed using the proposed control method. A new postfault modulation based on space vector modulation with virtual vectors is proposed. The feasibility of the proposed control method is verified by simulation and an experiment for one fault scenario in a three-level neutral-point-clamped inverter with a 3.73 kW motor load. Furthermore, this article contributes to improving the reliability of three-level inverters.

42 ENGINEERING↗

Simple and Robust Carrier-Based PWM Technique for Single-Stage Three-phase Rectifier Indirect Matrix Converter

Indirect matrix converters (IMC) can offer high efficiency, high power density, and bidirectional power flow capability with a single-stage three-to single-phase AC-AC power conversion integrating a conventional three-phase active rectifier with a primary side full-bridge inverter of a dual active bridge converter. However, the IMCs generally require space vector modulation techniques, leading to complex sectors and dwell times calculations. A practical implementation of the modulation methods with a commonly used digital signal processor becomes even more challenging when considering power factor correction, harmonics reduction, and deadtime between sector transitions. This paper proposes a simple and robust carrier-based pulse width modulation (PWM) technique determined through a voltage-source inverter (VSI) to current-source inverter (CSI) to IMC conversion. This translation enables the adoption of all conventional VSI control methods with active and reactive power control in the IMCs through simple carrier and reference waveform comparison. The VSI vectors are first one-on-one matched with CSI vectors and translated to IMC modulation signals without calculating sectors and dwell times. Nine different carrier waveforms are proposed, and the converter performance is analyzed. Grid current THD and efficiency are estimated for each modulation method. The symmetric A and B methods had the lowest THD of the grid current, 2.80%, and the efficiency remained at approximately 98.3%, making it the most suitable carrier-based method proposed in this paper. The space vector PWM (SVPWM) modulation method was implemented to the DSP and generated the expected twelve gate signals.

Benson, Mikayla↗

Thermal Stress Reduction in Power Switching Devices Using Distributed Loss PWM Concept for Current Source Inverters

A new modulation scheme is proposed for current source inverters (CSIs) that reduces the variation and peak junction temperature in the CSIs' power devices. The distributed loss pulse-width modulation (DLM) concept is introduced and applied to traditional space vector modulation methods to develop modified modulation schemes that reduce the thermal stress on power devices. The device junction temperatures resulting from conventional and DLM schemes are compared. Simulation and experimental results confirm that the proposed DLM concept reduces thermal stress on the devices while maintaining the same high output current waveform quality compared to traditional CSI modulation schemes. The CSI power device lifetime (i.e., the number of cycles to failure) are estimated using the simulation and experimental results. The proposed DLM significantly increases the device lifetime (by 5 to 6 times) by reducing the junction temperature variation compared to the conventional modulations.

42 ENGINEERING↗

Predictive Control to Further Reduce DC-Link Capacitor Current Stress for Segmented Inverter

Two three-phase interleaved inverters have been used in traction drive applications to reduce the current stress in a DC link capacitor bank. In such applications, either carrier-based or space vector modulation is used to select the optimum switching sequences, and the results show 50% less capacitor current than that of a single three-phase inverter. The switching state selection process for this inverter is tedious, and there has been no research to find the optimal switching state. To overcome this challenge, this research employed a simple finite set model predictive control to select the optimum switching sequence for a dual three-phase interleaved topology, called a segmented inverter. The results show that the predictive control algorithm can provide a simple solution and can reduce the current stress by 27% compared with traditional modulation techniques for the segmented inverters.

Ribeiro, Pedro↗

Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation

This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.

Lee, Sangwhee [ORNL] (ORCID:0000000335490057)↗

A Six-Phase Space Vector PWM Technique for Wide Bandgap Device-Based Three-Level Inverters

This article presents a space vector pulsewidth modulation (SVPWM) technique for wide bandgap (WBG) device-based three-level (3L) six-phase inverters. Implementation of the SVPWM techniques for any six-phase inverter is complex for its high number of possible voltage vectors. Different six-phase load configurations are also possible depending on the angle between two consecutive phases and neutral point connections. The implementation techniques change depending on the load configuration. Moreover, a common neutral point for all six phases leads to circulating currents. Capacitor voltage balancing is also needed for 3L inverters. Capacitor voltage balancing and addressing the circulating current problem further increases the implementation complexity. In this article, a generalized SVPWM technique is proposed for the six-phase 3L inverters that is implementable using two three-phase 3L SVPWM blocks. The SVPWM technique also ensures dc bus capacitor voltage balancing and minimizes circulating current. Here, the SVPWM technique is experimentally verified using a GaN-based 3L six-phase active neutral point clamped (ANPC) inverter prototype, and the results are presented in this article.

42 ENGINEERING↗

Enhanced Performance of Dual Inverter with a Floating Capacitor for Motor Drive Applications

This paper studies a dual inverter supplied by a DC-link and a floating capacitor (FC), emerged as a promising inverter topology for motor drive applications. For this type of inverter, the voltage ratio between the DC-link and the FC can be actively controlled. This ratio design is crucial as it essentially defines both the DC-link voltage utilization and the inverter output quality. Several voltage ratios have previously been discussed to enhance the dual inverter performance, but only one aspect, either the voltage utilization or the output quality, is investigated. As a result, although one performance aspect can be improved, the other aspect has been adversely affected. In this work, a comparative study considering both aspects is carried out for all the possible voltage ratios. Based on this analysis, the optimal ratios for different inverter modulation indices are identified. This is followed by proposing a ratio selection strategy to double the voltage utilization without degrading the output quality. Furthermore, this strategy enables an electric drive to work at a higher maximum speed without flux weakening for a given DC-link voltage. The claimed advantages have been proved by experimental tests on an open-end windings induction motor drive.

42 ENGINEERING↗

Stacked Low-Inertia Converter or Solid-State Transformer: Modeling and Model Predictive Priority-Shifting Control for Voltage Balance

This paper presents control challenges of stacked low-inertia converter (SLIC) or cascaded reduced dc-link solid-state transformer (SST) and proposes a novel model predictive priority-shifting (MPPS) control with implicit modulator and a discrete-time large-signal model for voltage balancing and dc-link regulation. Low-inertia converters, featuring small electrolytic capacitor-less dc links, dramatically reduce cost, size, and weight compared to conventional solutions. However, without a large dc-link buffer, the input and output are tightly coupled, leading to significant control challenges. The control becomes even more challenging with these converters stacked input-series output-parallel (ISOP) for medium-voltage (MV) grid, which causes coupling between the modules besides the coupling within each module. This paper analyzes the multi-objective, multi-degree of freedom control problem, using the modular soft-switching solid-state transformer (M-S4T) as an example of the SLIC. First, distribution of control efforts under controller saturation is critical because multiple control objectives can be conflicting, especially when the module voltages are unbalanced and are being restored. The MPPS can shift the priorities to address this issue. Second, due to the low inertia and high dc-link ripple, classic space vector pulse-width modulation (SVPWM), average model with small-ripple assumption, and control design based on small-signal model cannot accurately modulate, model, and control the nonlinear reduced dc link. Therefore, a discrete-time large-signal model of the M-S4T is established to derive the predictive control in the MPPS. The MPPS and the PI control are compared in MV simulations to show the issue of applying the PI to the SLIC and the effectiveness of the MPPS for voltage balancing and dc-link regulation in a deadbeat manner. Finally, the proposed control is tested on a 5 kV ISOP SiC SST prototype to verify priority shifting to address controller saturation issue and fast and robust voltage balancing.

14 SOLAR ENERGY↗

Electronic nature of chiral charge order in the kagome superconductor CsV 3 Sb 5

Kagome superconductors with T C up to 7 K have been discovered for over 40 y. Recently, unconventional chiral charge order has been reported in kagome superconductor KV 3 Sb 5 , with an ordering temperature of one order of magnitude higher than the T C . However, the chirality of the charge order has not been reported in the cousin kagome superconductor CsV 3 Sb 5 , and the electronic nature of the chirality remains elusive. In this paper, we report the observation of electronic chiral charge order in CsV 3 Sb 5 via scanning tunneling microscopy (STM). We observe a 2 × 2 charge modulation and a 1 × 4 superlattice in both topographic data and tunneling spectroscopy. 2 × 2 charge modulation is highly anticipated as a charge order by fundamental kagome lattice models at van Hove filling, and is shown to exhibit intrinsic chirality. We find that the 1 × 4 superlattices form various small domain walls, and can be a surface effect as supported by our first-principles calculations. Crucially, we find that the amplitude of the energy gap opened by the charge order exhibits real-space modulations, and features 2 × 2 wave vectors with chirality, highlighting the electronic nature of the chiral charge order. STM study at 0.4 K reveals a superconducting energy gap with a gap size 2Δ = 0.85 meV, which estimates a moderate superconductivity coupling strength with 2Δ/k B T C = 3.9. Furthermore, when further applying a c-axis magnetic field, vortex core bound states are observed within this gap, indicative of clean-limit superconductivity.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Structure of Charge Density Waves in La1.875Ba0.125CuO4

Although charge-density wave (CDW) correlations exist in several families of cuprate superconductors, they exhibit substantial variation in CDW wavevector and correlation length, indicating a key role for CDW-lattice interactions. We investigated this interaction in La1.875Ba0.125CuO4 using single crystal x-ray diffraction to collect a large number of CDW peak intensities, and determined the Cu and La/Ba atomic distortions induced by the formation of CDW order. Within the CuO2 planes, the distortions involve a periodic modulation of the Cu-Cu spacing along the direction of the ordering wave vector. The charge ordering within the copper-oxygen layer induces an out-of-plane breathing modulation of the surrounding lanthanum layers, which leads to a related distortion on the adjacent copper-oxygen layer. Our result implies that the CDW-related structural distortions do not remain confined to a single layer but rather propagate an appreciable distance through the crystal. This leads to overlapping structural modulations, in which CuO2 planes exhibit distortions arising from the orthogonal CDWs in adjacent layers as well as distortions from the CDW within the layer itself. We attribute this striking effect to the weak c-axis charge screening in cuprates and suggest this effect could help couple the CDW between adjacent planes in the crystal.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

The Subchalcogenides Ir 2 In 8 Q (Q = S, Se, Te): Dirac Semimetal Candidates with Re-entrant Structural Modulation

Subchalcogenides are uncommon compounds where the metal atoms are in unusually low formal oxidation states. They bridge the gap between intermetallics and semiconductors and can have unexpected structures and properties because of the exotic nature of their chemical bonding as they contain both metal–metal and metal–main group (e.g., halide, chalcogenide) interactions. Finding new members of this class of materials presents synthetic challenges as attempts to make them often result in phase separation into binary compounds. We overcome this difficulty by utilizing indium as a metal flux to synthesize large (millimeter scale) single crystals of novel subchalcogenide materials. Herein, we report two new compounds Ir 2 In 8 Q (Q = Se, Te) and compare their structural and electrical properties to the previously reported Ir 2 In 8 S analogue. Ir 2 In 8 Se and Ir 2 In 8 Te crystallize in the $P_{4_2}$/mnm space group and are isostructural to Ir2In8S, but also have commensurately modulated (with q vectors q = 1/6a* + 1/6b* and q = 1/10a* + 1/10b* for Ir 2 In 8 Se and Ir 2 In 8 Te, respectively) low-temperature phase transitions, where the chalcogenide anions in the channels experience a distortion in the form of In–Q bond alternation along the ab plane. Both compounds display re-entrant structural behavior, where the supercells appear on cooling but revert to the original subcell below 100 K, suggesting competing structural and electronic interactions dictate the overall structure. Notably, these materials are topological semimetal candidates with symmetry-protected Dirac crossings near the Fermi level and exhibit high electron mobilities (~1500 cm 2 V –1 s –1 at 1.8 K) and moderate carrier concentrations (~10 20 cm –3 ) from charge transport measurements. This work highlights metal flux as a synthetic route to high quality single crystals of novel intermetallic subchalcogenides with Dirac semimetal behavior.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

A Phase-Disposition PWM Enabled Model Predictive Control for a Nine-Level Inner-Interleaved Hybrid Multilevel Converter

This article brings forward a phase-disposition pulse width modulation enabled model predictive control (PDPWM-MPC) for a nine-level inner-interleaved hybrid multilevel converter (9L-IHMC). Firstly, three layers of virtual space vector diagrams (VSVD) are established based on the sign patterns of the original and virtual reference vectors in the abcframe, respectively, to achieve the phase-disposition pulse width modulation (PD-PWM) in a non-independent three-phase way. Then, three adjacent virtual vectors in the third-layer VSVD, together with their optimized duty cycles, are applied to guarantee the optimal current tracking. Finally, through the use of the duty cycle alternation approach, dc-link and floating capacitors voltages are balanced and circulating currents are mitigated as well. The proposed PDPWM-MPC can not only enable the decoupling of the low-and high-frequency stages in the 9L-IHMC, but also reduce both output current ripples and computational burden. In addition, it can achieve a constant equivalent switching frequency and address the disproportion of power losses associated with the PD-PWM. Here, both simulations and experiments on a silicon carbide device-based prototype substantiate the effectiveness of the proposed control strategy.

42 ENGINEERING↗

ModuleOT: A Hardware Security Module for Operational Technology: Preprint

With increasing penetration levels of distributed energy resources (DERs) on the distribution grid, as well as new technological advancements in the cyber space, new cyberattack vectors are being introduced, and the available attack surface is constantly increasing. Despite this increasing risk, the standard IEEE 1547-2018 does not yet recommend cybersecurity measures for DERs. To address this and to better protect data on the distribution grid - from the standpoints information security as well as operational security - ModuleOT has been developed. The module aims to significantly reduce cyberattack vectors by improving data privacy for user applications. This is accomplished by performing the core functions of encryption, authentication, authorization, certificate management, and user access control. The module integrates a custom security application with hardware cryptographic acceleration. The application secures all communications using Transmission Control Protocol over Internet Protocol (TCP/IP). These include the three most commonly used communications protocols for power systems information exchange: Modbus, Distributed Network Protocol 3 (DNP3), and Smart Energy Profile 2.0 (SEP2.0). These three protocols are also supported by IEEE 1547-2018 for all DER devices. This paper tests the data encryption/decryption feature on a physical networking test bed with emulated Modbus devices reporting grid data and presents the results.

24 POWER TRANSMISSION AND DISTRIBUTION↗

2D Homologous Series SrFM n BiS n +2 (M = Pb, Ag 0.5 Bi 0.5 ; n = 0, 1) and Commensurately Modulated Sr 2 F 2 Bi 2/3 S 2

In this work, we report three new mixed-anion two-dimensional (2D) compounds: SrFPbBiS 3 , SrFAg 0.5 Bi 1.5 S 3 , and Sr 2 F 2 Bi 2/3 S 2 . Their structures as well as the parent compound SrFBiS 2 were refined using single-crystal X-ray diffraction data, with the sequence of SrFBiS 2 , SrFPbBiS 3 , and SrFAg 0.5 Bi 1.5 S 3 defining the new homologous series SrFM n BiS n+2 (M = Pb, Ag 0.5 Bi 0.5 ; n= 0, 1). Sr 2 F 2 Bi 2/3 S 2 has a different structure, which is modulated with a q vector of 1/3b* and was refined in superspace group X2/m(0 β 0)00 as well as in the 1x3x1 superstructure with space group C2/m (with similar results). Sr 2 F 2 Bi 2/3 S 2 features hexagonal layers of alternating [Sr 2 F 2 ] 2+ and [Bi 2/3 S 2 ] 2- , and the modulated structure arises from the unique ordering pattern of Sr 2+ cations. SrFPbBiS 3 , SrFAg 0.5 Bi 1.5 S 3 , and Sr 2 F 2 Bi 2/3 S 2 are semiconductors with band gaps of 1.31, 1.21, and 1.85 eV, respectively. The latter compound exhibits room temperature red photoluminescence at ~ 700 nm.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

STSR-INR: Spatiotemporal super-resolution for multivariate time-varying volumetric data via implicit neural representation

Implicit neural representation (INR) has surfaced as a promising direction for solving different scientific visualization tasks due to its continuous representation and flexible input and output settings. We present STSR-INR, an INR solution for generating simultaneous spatiotemporal super-resolution for multivariate time-varying volumetric data. Inheriting the benefits of the INR-based approach, STSR-INR supports unsupervised learning and permits data upscaling with arbitrary spatial and temporal scale factors. Unlike existing GAN- or INR-based super-resolution methods, STSR-INR focuses on tackling variables or ensembles and enabling joint training across datasets of various spatiotemporal resolutions. Here we achieve this capability via a variable embedding scheme that learns latent vectors for different variables. In conjunction with a modulated structure in the network design, we employ a variational auto-decoder to optimize the learnable latent vectors to enable latent-space interpolation. To combat the slow training of INR, we leverage a multi-head strategy to improve training and inference speed with significant speedup. We demonstrate the effectiveness of STSR-INR with multiple scalar field datasets and compare it with conventional tricubic+linear interpolation and state-of-the-art deep-learning-based solutions (STNet and CoordNet).

97 MATHEMATICS AND COMPUTING↗