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Results for “subthreshold swing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

High Mobility, High Carrier Density SnSe 2 Field‐Effect Transistors with Ultralow Subthreshold Swing and Gate‐Controlled Photoconductance Switching

2D and layered semiconductors are considered as promising electronic materials, particularly for applications that require high carrier mobility and efficient field-effect switching combined with mechanical flexibility. To date, however, the highest mobility has been realized primarily at low carrier concentration. Here, it is shown that few-layer/multilayer SnSe 2 gated by a solution top gate combines very high room-temperature electron mobility (up to 800 cm 2 V −1 s −1 ), along with large on-off current ratios (>10 5 ) and a subthreshold swing below the thermodynamic limit (50 mV per decade) in field-effect devices, at exceptionally large sheet carrier concentrations of ≈10 13 cm −2 . Observed mobility enhancements upon partial depletion of the channel point to near-surface defects or impurities as the mobility-limiting scattering centers. Under illumination, the resulting gap states give rise to gate-controlled switching between positive and negative photoconductance. The results qualify SnSe 2 as a promising layered semiconductor for flexible and wearable electronics, as well as for the realization of advanced approaches to photodetection.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Size Effect of Negative Capacitance State and Subthreshold Swing in Van der Waals Ferrielectric Field–Effect Transistors

Analytical calculations corroborated by the finite element modeling show that thin films of Van der Waals ferrielectrics covered by a 2D-semiconductor are promising candidates for the controllable reduction of the dielectric layer capacitance due to the negative capacitance (NC) effect emerging in the thin films. The NC state is conditioned by energy-degenerated poly-domain states of the ferrielectric polarization induced in the films under incomplete screening conditions in the presence of a dielectric layer. Calculations performed for the FET-type heterostructure “ferrielectric CuInP 2 S 6 film—2D-MoS 2 single-layer—SiO 2 dielectric layer” reveal the pronounced size effect of the multilayer capacitance. Derived analytical expressions for the electric polarization and multilayer capacitance allow to predict the thickness range of the dielectric layer and ferrielectric film for which the NC effect is the most pronounced in various Van der Waals ferrielectrics, and the corresponding subthreshold swing becomes much less than the Boltzmann's limit. Obtained results can be useful for the size and temperature control of the NC effect in the steep-slope ferrielectric FETs.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Negative Capacitance MgZnO-Channel Thin-Film Transistor With Ferroelectric NiMgZnO in the Gate Stack

We demonstrate the negative capacitance thin-film transistor (NC-TFT) on glass substrate using the multifunctional MgZnO (MZO). The Mg 0.03 Zn 0.97 O semiconductor layer acts as the TFT channel for stable operation while the Ni-doped MZO, i.e. Ni 0.02 Mg 0.15 Zn 0.83 O (NMZO) serves as the ferroelectric layer in the NMZO/SiO 2 stacking gate dielectric structure. The subthreshold swing (SS) value is significantly reduced over the reference TFT without ferroelectric layer. The minimum SS value of the NC-TFT reaches 52 mV/dec while the on/off ratio of drain current ID reaches 10 9 .

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2020

Ultra‐Steep Slope Impact Ionization Transistors Based on Graphene/InAs Heterostructures

With the continued scaling of transistors, there is a growing trend for developing steep slope transistors with subthreshold swing (SS) below Boltzmann limitation ( k T/ q ). To this end, impact ionization metal oxide semiconductor (I‐MOS) transistors are attractive for a unique combination of high ON‐state current density, small hysteresis, and ultra‐steep SS slope. However, the performance of I‐MOS is generally limited by the relatively thick depletion region and large operation voltage required for the activation of impact ionization (typically >5 V). Herein, a high‐performance I‐MOS is constructed by van der Waals integrating single‐crystal InAs film with graphene. Due to the low bandgap of InAs as well as the semi‐metallic nature of graphene, the InAs/graphene I‐MOS demonstrates a low operation voltage of 1.5 V, high ON‐state current of 230 μA μm −1 , steep SS <0.6 mV dec −1 , and large ON–OFF ratio >10 6 at temperature below 200 K. Furthermore, a negative transconductance and steep current oscillation is observed in the subthreshold regime, and a device working mechanism is proposed for this novel phenomenon. This study not only pushes the performance limit of I‐MOS but also defines a general pathway to van der Waals heterostructures between conventional III–V compound semiconductors and novel 2D materials for unconventional device functions.

Liu, Yuan↗
DOE OSTI2023

Mitigating Heavy Ion Irradiation‐Induced Degradation in p‐type SnO Thin‐Film Transistors at Room Temperature

The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au 4+ irradiation at a fluence level of 5.2 × 10 12 ions cm −2 , the output drain current and on/off current ratio ( I on / I off ) decrease by more than one order of magnitude, field‐effect mobility ( μ FE ) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 10 5 A cm −2 , approximately four times increase in I on / I off is observed, 41% increase in μ FE , and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique.

Al-Mamun, Nahid Sultan↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2024

Improving 2D Schottky contacts using an intralayer strategy

An additional insulating layer between the electrode and semiconductor is beneficial to reduce the interfacial coupling and build two-dimensional (2D) Schottky contacts. Here, an intralayer strategy was proposed by using metallic 2D Bi 2 Sr 2 CaCu 2 O 8+δ (BSCCO) as contacts on 2D semiconductors. Inside a BSCCO monolayer, a conductive layer is sandwiched between insulating layers. Thus, the BSCCO contact has its own insulating layer, which is ultra-thin, single crystalline, and of high quality. This native layer could reduce the metal-induced gap state and thus weaken the interfacial Fermi level pinning effect. Such 2D Schottky diodes thus have barrier heights of 300 mV and a rectification ratio of 104. Furthermore, 2D metal-semiconductor field-effect transistors with BSCCO Schottky gate have a high on-off ratio, low leakage current, and low subthreshold swing value near the theoretical limit. The intralayer structure offers a new approach to improve the 2D Schottky junctions and has prospects in 2D electronics and optoelectronics.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Phase transition in two-dimensional monolayer (1L)-molybdenum disulfide induced by atomic S-basal plane gliding via synchrotron X-ray monochromatic beam radiation for superior electronic performance

Here, in this work, we report a novel approach to reduce the channel resistance by inducing a phase transition behavior from 2H to 1T in a monolayer MoS 2 (1L-MoS 2 ) by a synchrotron X-ray monochromatic beam (mono-beam) radiation. The effects of the biphase structure by the mono-beam on the 1L-MoS2 film were investigated using Raman spectra, photoluminescence (PL) spectra, scanning tunneling microscopy, and scanning tunneling spectroscopy, respectively. Through material characterization, we identified that the lateral sliding of S-vacancies along the S-plane in the 1L-MoS 2 is the key reason for the origin of unidirectional phase transition. The precise phase engineering triggered by the mono-beam radiation process allows the realization of field-effect transistors (FET) with 2X improvement in mobility toward a high on/off ratio (~10 8 ) and a near-ideal subthreshold swing of ~88 mV per decade. The validity of the phase engineering could be further extended for its application as a memory device, exhibiting a gate tunable conduction modulation behavior and a high resistance ratio of ~10 2 at a gate bias of 5 V with endurance of ~100 cycles. Furthermore, an artificial neural network using the synaptic weight update with accuracy of ~93 % was achieved.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Organic thin-film transistors with a bottom bilayer gate dielectric having a low operating voltage and high operational stability

This study reports on p-channel bottom-gate organic thin-film transistors (OTFT) that achieve low-voltage operation with a thin bilayer gate dielectric of CYTOP/HfO 2 that also leads to high operational stability. A bottom-gate geometry allows the thickness of the gate dielectric to be reduced to 17 nm, thereby increasing the gate dielectric capacitance density to a value of up to 258 nF/cm 2 . All OTFTs yielded threshold voltages (V TH ) lower than -1 V, thereby providing minimum operating voltage (gate to source voltage ~ V TH ) of -1 V with field-effect mobility values in the range from 0.3 to 0.8 cm 2 /Vs and subthreshold swing values below 100 mV/dec. Operational stability during DC bias stress was found similar to that measured in devices with a top-gate geometry, with about 1% of drain current change after 6 h. Here, using a double-stretched exponential function, the operational stability characteristics were modeled. It was found that by increasing the metal oxide layer thickness, the threshold voltage can shift toward positive values under DC stress tests. For CYTOP layer thicknesses above 15 nm, a thicker CYTOP layer was found to shift the threshold voltage in the opposite direction toward negative values. Furthermore, these p-channel bottom-gate organic transistor with a bilayer gate dielectric of CYTOP/HfO 2 combine high mobility, high operational stability, and lower voltage operation of -1 V compared to top-gate OTFTs.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor

The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.

high-κ membrane↗
DOE OSTI2019

Evaporated tellurium thin films for p-type field-effect transistors and circuits

There is an emerging need for semiconductors that can be processed at near ambient temperature with high mobility and device performance. Although multiple n-type options have been identified, the development of their p-type counterparts remains limited. In this paper, we report the realization of tellurium thin films through thermal evaporation at cryogenic temperatures for fabrication of high-performance wafer-scale p-type field-effect transistors. We achieve an effective hole mobility of ~35 cm 2 V –1 s –1 , on/off current ratio of ~10 4 and subthreshold swing of 108 mV dec –1 on an 8-nm-thick film. High-performance tellurium p-type field-effect transistors are fabricated on a wide range of substrates including glass and plastic, further demonstrating the broad applicability of this material. Significantly, three-dimensional circuits are demonstrated by integrating multi-layered transistors on a single chip using sequential lithography, deposition and lift-off processes. Finally, various functional logic gates and circuits are demonstrated.

42 ENGINEERING↗
DOE OSTI2024

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS 2 transistors back-gated by single-layer polycrystalline PbZr 0.35 Ti 0.65 O 3 . The devices exhibit current switching ratios up to 8 × 10 6 within an ultra-low gate voltage window of $$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V g = ± 0.5 V and subthreshold swing (SS) as low as 9.7 mV decade −1 at room temperature, transcending the 60 mV decade −1 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Reversible writing of high-mobility and high-carrier-density doping patterns in two-dimensional van der Waals heterostructures

A key feature of two-dimensional materials is that the sign and concentration of their carriers can be externally controlled with techniques such as electrostatic gating. However, conventional electrostatic gating has limitations, including a maximum carrier density set by the dielectric breakdown, and ionic liquid gating and direct chemical doping also suffer from drawbacks. In this work, we show that an electron-beam-induced doping technique can be used to reversibly write high-resolution doping patterns in hexagonal boron nitride-encapsulated graphene and molybdenum disulfide (MoS 2 ) van der Waals heterostructures. The doped MoS 2 device exhibits an order of magnitude decrease of subthreshold swing compared with the device before doping, whereas the doped graphene devices demonstrate a previously inaccessible regime of high carrier concentration and high mobility, even at room temperature. We also show that the approach can be used to write high-quality p–n junctions and nanoscale doping patterns, illustrating that the technique can create nanoscale circuitry in van der Waals heterostructures.

36 MATERIALS SCIENCE↗
DOE OSTI2021

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ~5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10 –8 mA/mm, a high on/off current ratio of 10 9 , a threshold voltage of –2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of –2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (D it ) is estimated to be less than 8.49 × 10 11 cm –2 eV –1 . Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Quantitative characterization of ZrO2 gate dielectric interface with tellurium

Tellurium (Te) has recently emerged as a promising p-type semiconductor that can be processed at low temperatures, compatible with back end of line CMOS integration. Characterization of tellurium–dielectric interfaces is essential for further device advancements. Here, the interface quality of Te with ZrO2 gate dielectric is studied in a metal-oxide semiconductor capacitor structure. The interface trap density (Dit) is measured as a function of atomic layer deposition (ALD) temperature, without the use of a seed layer. Given the low thermal budget of Te, the ALD temperature is shown to be particularly important. The lowest Dit of 5 × 1012 states/cm2 eV is obtained at a low ALD process temperature of 120 °C. To further assess the impact of Dit on device performance, field-effect transistors (FETs) were fabricated. The subthreshold swing and effective hole mobility of the FETs were analyzed in relation to Dit, emphasizing the importance of a defect-minimized interface for enhancing Te transistor performance.

Byeon, Kyeong-Jae↗