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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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9 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

2 kV, 0.7 mΩ•cm2 Vertical Ga2O3 Superjunction Schottky Rectifier with Dynamic Robustness

We report the first experimental demonstration of a vertical superjunction device in ultra-wide bandgap (UWBG) Ga 2 O 3 . The device features 1.8 μm wide, 2×10 17 cm -3 doped n-Ga 2 O 3 pillars wrapped by the charge-balanced p-type nickel oxide (NiO). The sidewall NiO is sputtered through a novel self-align process. Benefited from the high doping in Ga 2 O 3 , the superjunction Schottky barrier diode (SJ-SBD) achieves a ultra-low specific on-resistance (R ON,SP ) of 0.7 mΩ•cm 2 with a low turn-on voltage of 1 V and high breakdown voltage (BV) of 2000 V. The R ON,SP ~BV trade-off is among the best in all WBG and UWBG power SBDs. The device also shows good thermal stability with BV > 1.8 kV at 175 °C. In the unclamped inductive switching tests, the device shows a dynamic BV of 2.2 kV and no degradation under 1.7 kV repetitive switching, verifying the fast acceptor depletion in NiO under dynamic switching. Such high-temperature and switching robustness are reported for the first time in a heterogeneous superjunction. These results show the great potential of UWBG superjunction power devices.

Qin, Yuan↗
DOE OSTI2024

Vertical GaN Superjunction Diode on Sapphire with Kilovolt Dynamic Breakdown Voltage

The development of superjunction structures for use in vertical wide bandgap power devices promise to break the 1-D material limits. Additionally, the possibility of utilizing heteroepitaxial GaN-on-Sapphire wafer for vertical devices can significantly trim the material and device cost. This work introduces a quasi-vertical GaN-on-Sapphire superjunction PN diode design utilizing sputtered p-NiO on the etched GaN fins for superjunction formation. DC breakdown voltage is shown to vary with superjunction charge imbalance and significantly exceed the expected 1-D planar limit of 350V given the epilayer design used. A maximum breakdown voltage of 840 V is extracted for near charge balance conditions limited by leakage current. Dynamic breakdown of the device is characterized as a function of reverse voltage slew rate. A maximum dynamic breakdown voltage of 1160 V under a reverse voltage slew rate of 2000 V/μs is found.

Porter, Matthew↗
DOE OSTI2023

1 kV Self-Aligned Vertical GaN Superjunction Diode

This work demonstrates vertical GaN superjunction (SJ) diodes fabricated via a novel self-aligned process. The SJ comprises n-GaN pillars wrapped by the charge-balanced p-type nickel oxide (NiO). After the NiO sputtering around GaN pillars, the self-aligned process exposes the top pillar surfaces without the need for additional lithography or a patterned NiO etching which is usually difficult. The GaN SJ diode shows a breakdown voltage (B V) of 1100 V, a specific on-resistance (R ON ) of 0.4 mΩ· cm2, and a SJ drift-region resistance ( R dr ) of 0.13 mΩ· cm2. Further, the device also exhibits good thermal stability with B V retained over 1 kV and R ON dropped to 0.3 mΩ· cm2 at 125°C. The trade-off between B V and R dr is superior to the 1D GaN limit. These results show the promise of vertical GaN SJ power devices. The self-aligned process is applicable for fabricating the heterogeneous SJ based on various wide- and ultra-wide bandgap semiconductors.

42 ENGINEERING↗
NASA NTRSDate not supplied

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage. The SEB threshold voltage varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of SEB threshold voltage is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new figure of merit (FOM), which accounts for the tradeoff between SEB threshold voltage and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FOM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

SiC↗
NASA NTRS2022

Simulation-based Study of Single-Event Burnout in 4H-SiC High-Voltage Vertical Superjunction DMOSFET: Physical Failure Mechanism and Robustness vs. Performance Tradeoffs

We explore and elucidate physical failure mechanisms in a 4H-SiC, high voltage, superjunction (SJ) vertical DMOSFET from a single heavy ion strike using three-dimensional electro-thermal transient simulations. The single-event burnout (SEB) failure is thermal runaway from second breakdown, initiated by impact ionization and terminated with mesoplasma formation, at the center of the P-pillar/N+ substrate interface. We also demonstrate that the SEB performance of this SiC SJ DMOSFET is insensitive to the pillar width but sensitive to the strike location with ion strike at the P-pillar causing SEB at a lower blocking voltage than at the N-pillar. Compared to commercially available 1.2 kV blocking-rated non-SJ DMOSFETs, which have been demonstrated to survive SEB up to 525 V, the SJ DMOSFET increases SEB survival threshold voltage (VSEB) by a factor of 2.2, making it close to 1200 V, while the on-resistance is increased by only 11%. Using our recently developed figure of merit (FoM), which considers the trade-off between VSEB and on-state performance, we find that the SiC SJ DMOSFET achieves a FoM that is 14 times better, making it superior to conventional 1.2 kV SiC DMOSFETs for long-term radiation-tolerant operation in space applications.

Silicon Carbide↗
DOE OSTI2026

GaN Core-shell Nanofin Vertical Transistor (CoNVerT): A New Direction for Power Electronics (Final Scientific/Technical Report)

A novel power transistor architecture, the GaN c ore-shell n anofin ver tical transistor (CoNVerT) to address fundamental challenges in realizing the ultimate limit of GaN power transistor performance was explored experimentally. This technology promises ultra-high-efficiency high voltage/high power applications (e.g. DC/DC converters, motor control, fast charging, actuation), as well as to operate in harsh environments. The device exploits a vertical superjunction structure based on an experimentally-validated core-shell nanofin growth process in which lateral p-n heterojunctions are formed in a single growth step, while still maintaining vertical current flow for compact die size and low cost. The concept leverages the best properties of GaN for mid-range voltage applications: high mobility, high breakdown voltage, and native heterojunction enhancement-mode operation. Due to the crystallographic nature of the nanofin growth by molecular beam epitaxy, the sidewall heterojunctions occur on non-polar planes, resulting in ultra-smooth interfaces for high mobility, no sidewall etch damage and related surface/interface states, and elimination of piezoelectric effects that can limit reliability in conventional structures. This also facilitates superjunction formation for maximum device performance, and the selective-area growth of the nanofin results in dislocation-free growth, even on low-cost Si (111) substrate. In this program, core-shell nanofins were grown by molecular beam epitaxy, test structures to evaluate the doping, resistivity, and other electrical properties were fabricated, and the material and test structures were characterized in detail. The work identified clear potential (e.g., the doping was well controlled as required for superjunction concepts), but also additional areas that require additional effort to resolve (some unexpected crystal defects were encountered that require additional engineering to overcome). Simulation studies of the proposed concept validate that the fundamental approach is very promising, but additional effort in experimental realization is needed.

42 ENGINEERING↗
DOE OSTI2024

Analysis of strain in ion implanted 4H-SiC by fringes observed in synchrotron X-ray topography

A novel high energy implantation system has been successfully developed to fabricate 4H-SiC superjunction devices for medium and high voltage via implantation of dopant atoms with multi-energies ranging from 13 to 66 MeV. The significantly higher levels of energy used compared to conventional implantation processes, necessitates detailed characterization of the lattice damage caused by implantation. To achieve this by employing the novel high energy system, 4H-SiC wafer with 12 μm epilayers were blanket implanted by 13.8–65.7 MeV Al atoms. The lattice damages induced by the implantation were primarily characterized by Synchrotron X-ray Plane Wave Topography (SXPWT) and Reciprocal Space Mapping (RSM). Topographs reveal fringe contrast akin to multiple asymmetric diffraction peaks with an angular separation of only 2″ (arcseconds) observed on rocking curves, indicating inhomogeneous strain distribution across the implanted layer. The strain profile of the implanted layer was extracted from the fringe contrast by applying Rocking-curve Analysis by Dynamical Simulation (RADS). In conclusion, the maximum strain value is similar to that measured on the RSM.

A1. Characterization↗
DOE OSTI2026

AlGaN/GaN Core-Shell Nanofin Diodes on Si Substrates for Vertical GaN Electronics

We demonstrate plasma-assisted MBE selective-area growth of GaN/AlGaN core-shell structures on Si(111) as a path to vertical GaN devices. The selective-area growth enables the full vertical and uniform core-shell fin structures to be realized in a continuous growth without breaking vacuum. TEM images and EDS mapping of the core-shell structures show well-aligned crystal structure and sharp heterointerfaces. Dislocation filtering was observed in STEM imaging of the fin structure. P-N junction diodes fabricated with GaN/AlGaN core-shell structures reveal ideality factors as low as 1.5, and the reverse-bias leakage is consistent with trap-assisted space-charge-limited conduction. While practical challenges exist, including material-related leakage, growth-related challenges and optimization, this demonstration of p-n junction by this method may provide a path to vertical Superjunction device concepts in GaN and related materials.

Xiong, Juncheng [University of Notre Dame, IN (Uni↗
NASA NTRS2013

Recent Radiation Test Results for Power MOSFETs

Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.

Lauenstein, Jean-Marie↗