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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Missileborne Artificial Vision System (MAVIS)

Several years ago when INTEL and China Lake designed the ETANN chip, analog VLSI appeared to be the only way to do high density neural computing. In the last five years, however, digital parallel processing chips capable of performing neural computation functions have evolved to the point of rough equality with analog chips in system level computational density. The Naval Air Warfare Center, China Lake, has developed a real time, hardware and software system designed to implement and evaluate biologically inspired retinal and cortical models. The hardware is based on the Adaptive Solutions Inc. massively parallel CNAPS system COHO boards. Each COHO board is a standard size 6U VME card featuring 256 fixed point, RISC processors running at 20 MHz in a SIMD configuration. Each COHO board has a companion board built to support a real time VSB interface to an imaging seeker, a NTSC camera, and to other COHO boards. The system is designed to have multiple SIMD machines each performing different corticomorphic functions. The system level software has been developed which allows a high level description of corticomorphic structures to be translated into the native microcode of the CNAPS chips. Corticomorphic structures are those neural structures with a form similar to that of the retina, the lateral geniculate nucleus, or the visual cortex. This real time hardware system is designed to be shrunk into a volume compatible with air launched tactical missiles. Initial versions of the software and hardware have been completed and are in the early stages of integration with a missile seeker.

Andes, David K.↗
NASA NTRS2012

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

High temperature↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

electronic packaging↗
NASA NTRS2003

Closed-Loop Performance Measures for Flight Controllers Subject to Neutron-Induced Upsets

It has been observed that atmospheric neutrons can produce single event upsets in digital flight control hardware. The phenomenon has been studied extensively at the chip level, and now system level experiments are underway. In this paper analytical closed-loop performance measures for the tracking error are developed for a plant that is stabilized by a recoverable computer system subject to neutron induced upsets. The underlying model is a Markov jump-linear system with process noise. The steady-state tracking error is expressed in terms of a generalized observability Gramian.

Gray, W. Steven↗
NASA NTRS2000

Deep Space Systems Technology Program Future Deliveries

NASA is in a period of frequent launches of low cost deep space missions with challenging performance needs. The modest budgets of these missions make it impossible for each to develop its own technology, therefore, efficient and effective development and insertion of technology for these missions must be approached at a higher level than has been done in the past. The Deep Space Systems Technology Program (DSST), often referred to as X2000, has been formed to address this need. The program is divided into a series of "Deliveries" that develop and demonstrate a set of spacecraft system capabilities with broad applicability for use by multiple missions. The First Delivery Project, to be completed in 2001, will provide a one MRAD-tolerant flight computer, power switching electronics, efficient radioisotope power source, and a transponder with services at 8.4 GHz and 32 GHz bands. Plans call for a Second Delivery in late 2003 to enable complete deep space systems in the 10 to 50 kg class, and a Third Delivery built around Systems on a Chip (extreme levels of electronic and microsystems integration) around 2006. Formulation of Future Deliveries (past the First Delivery) is ongoing and includes plans for such developments as highly miniaturized digital/analog/power electronics, optical communications, multifunctional structures, miniature lightweight propulsion, advanced thermal control techniques, highly efficient radioisotope power sources, and a unified flight ground software architecture to support the needs of future highly intelligent space systems. All developments are targeted at broad applicability and reuse, and will be commercialized within the US.

Salvo, Christopher G.↗
NASA NTRS2021

Thermal Systems Modeling of Chemical Integrated Power Source (CHIPS) to Survive Lunar Night Environments

This paper presents the results of the systems level thermal modeling for a conceptual Chemical Heat Integrated Power Source (CHIPS). This proposed system offers a combined thermal and electrical power source to support survival of spacecraft operating in extreme low temperature lunar environments, without the use of radioisotope-based sources. A conceptual design study has been completed for this system, that uses heat generated by an exothermic chemical reaction in place of radioisotope or electrical heat sources. The goal of the study was to evaluate the feasibility of such as system through thermodynamic and chemical analysis and thermal modeling, and to identify technology gaps to inform a technology development and maturation plan. The specific technical objectives focused on delivery of 90-100 Wth thermal power and 30-40 We electrical power for 336 hours to a representative Commercial Lunar Payload Services (CLPS) lander, to support lunar surface survival and limited operations through a lunar night. The total system mass was targeted at ≤50 kg. A highly exothermic chemical reaction system is used to generate on-board electrical power for spacecraft systems, and thermal power to maintain critical spacecraft/lander systems within their allowable flight temperature (AFTs). Based on the very high energy content of the chemical reaction system, a much higher amount of heat per unit mass can be delivered to the spacecraft, relative to a rechargeable lithium-ion battery and electrical heater(s). Since radioisotope heaters or generators are not used, the system will be orders of magnitude lower in cost than a radioisotope heating/power unit, without the attendant regulatory complexities. As part of the CHIPS concept, a fraction of the thermal power generated is converted to electrical power via an appropriate thermal-to-electric converter technology (such as a free piston Stirling converter or a thermoelectric generator module), to provide power to critical loads. This approach is ideally suited to support operation of commercial landers (e.g., via the CLPS program). In most cases, these landers are only designed to operate during a portion of the lunar day, with no provision for survival through the lunar night. By supporting lunar night survival, a mission can be extended through the lunar night and at least into another lunar day, thus turning a nominal eight-day mission into a 36-day mission. Therefore, the current system demonstration will focus on scalability to support at least 336 hours (one lunar night) of continuous thermal and electrical power generation. Although initially targeted to support lunar equatorial landings, the technology is extensible to missions at the lunar poles, other extreme environments in the Solar System or even air-independent applications on Earth (e.g., ocean exploration).

West, William↗
NASA NTRS2021

Thermal Systems Modeling of Chemical Heat Integrated Power Source (CHIPS) to Survive Lunar Night Environments

This paper presents the results of the systems level thermal modeling for a conceptual Chemical Heat Integrated Power Source (CHIPS). This proposed system offers a combined thermal and electrical power source to support survival of spacecraft operating in extreme low temperature lunar environments, without the use of radioisotope-based sources. A conceptual design study has been completed for this system, that uses heat generated by an exothermic chemical reaction in place of radioisotope or electrical heat sources. The goal of the study was to evaluate the feasibility of such a system through thermodynamic and chemical analysis and thermal modeling, and to identify technology gaps to inform a technology development and maturation plan. The specific technical objectives focused on delivery of 90 to 100 Wth thermal power and 30 to 40 We electrical power for 336 hours to a representative Commercial Lunar Payload Services (CLPS) lander, to support lunar surface survival and limited operations through a lunar night. The total system mass was targeted at ≤50 kg. A highly exothermic chemical reaction system is used to generate on-board electrical power for spacecraft systems, and thermal power to maintain critical spacecraft/lander systems within their allowable flight temperature (AFTs). Based on the very high energy content of the chemical reaction system, a much higher amount of heat per unit mass can be delivered to the spacecraft, relative to a rechargeable lithium-ion battery and electrical heater(s). Since radioisotope heaters or generators are not used, the system will be orders of magnitude lower in cost than a radioisotope heating/power unit, without the attendant regulatory complexities. As part of the CHIPS concept, a fraction of the thermal power generated is converted to electrical power via an appropriate thermal-to-electric converter technology (such as a free piston Stirling converter or a thermoelectric generator module), to provide power to critical loads. This approach is ideally suited to support operation of commercial landers (e.g., via the CLPS program). In most cases, these landers are only designed to operate during a portion of the lunar day, with no provision for survival through the lunar night. By supporting lunar night survival, a mission can be extended through the lunar night and at least into another lunar day, thus turning a nominal eight-day mission into a 36-day mission. Therefore, the current system demonstration will focus on scalability to support at least 336 hours (one lunar night) of continuous thermal and electrical power generation. Although initially targeted to support lunar equatorial landings, the technology is extensible to missions at the lunar poles, other extreme environments in the Solar System or even air-independent applications on Earth (e.g., ocean exploration).

West, William↗
NASA NTRS1993

Design for testability and diagnosis at the system-level

The growing complexity of full-scale systems has surpassed the capabilities of most simulation software to provide detailed models or gate-level failure analyses. The process of system-level diagnosis approaches the fault-isolation problem in a manner that differs significantly from the traditional and exhaustive failure mode search. System-level diagnosis is based on a functional representation of the system. For example, one can exercise one portion of a radar algorithm (the Fast Fourier Transform (FFT) function) by injecting several standard input patterns and comparing the results to standardized output results. An anomalous output would point to one of several items (including the FFT circuit) without specifying the gate or failure mode. For system-level repair, identifying an anomalous chip is sufficient. We describe here an information theoretic and dependency modeling approach that discards much of the detailed physical knowledge about the system and analyzes its information flow and functional interrelationships. The approach relies on group and flow associations and, as such, is hierarchical. Its hierarchical nature allows the approach to be applicable to any level of complexity and to any repair level. This approach has been incorporated in a product called STAMP (System Testability and Maintenance Program) which was developed and refined through more than 10 years of field-level applications to complex system diagnosis. The results have been outstanding, even spectacular in some cases. In this paper we describe system-level testability, system-level diagnoses, and the STAMP analysis approach, as well as a few STAMP applications.

Simpson, William R.↗
NASA NTRS1986

Error propagation in a digital avionic processor: A simulation-based study

An experimental analysis to study error propagation from the gate to the chip level is described. The target system is the CPU in the Bendix BDX-930, an avionic miniprocessor. Error activity data for the study was collected via a gate-level simulation. A family of distributions to characterize the error propagation, both within the chip and at the pins, was then generated. Based on these distributions, measures of error propagation and severity were defined. The analysis quantifies the dependency of the measured error propagation on the location of the fault and the type of instruction/microinstruction executed.

Lomelino, D.↗
NASA NTRS2006

Extreme Temperature Electronics Using a Reconfigurable Analog Array

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. Previous work presented a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. This work describes a new reconfigurable analog chip developed by JPL and SPAWAR that is targeted for extreme temperature and evolutionary hardware experiments. Being based on Gm-C technology, this chip can have its functionality tuned and adapted to extreme temperatures through voltage bias adjustment. This tuning process will be controlled by Evolutionary Algorithms. This paper presents details of the reconfigurable analog chip as well as a system level overview. Some early experiments are also described.

evolvable hardware↗
NASA NTRS1997

Hierarchical Simulation to Assess Hardware and Software Dependability

This thesis presents a method for conducting hierarchical simulations to assess system hardware and software dependability. The method is intended to model embedded microprocessor systems. A key contribution of the thesis is the idea of using fault dictionaries to propagate fault effects upward from the level of abstraction where a fault model is assumed to the system level where the ultimate impact of the fault is observed. A second important contribution is the analysis of the software behavior under faults as well as the hardware behavior. The simulation method is demonstrated and validated in four case studies analyzing Myrinet, a commercial, high-speed networking system. One key result from the case studies shows that the simulation method predicts the same fault impact 87.5% of the time as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. Of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulations was therefore reduced from 500 to 145. Finally, the case studies show how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injections into the real system.

Ries, Gregory Lawrence↗
NASA NTRS2013

Packaging Technologies for 500C SiC Electronics and Sensors

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Chen, Liang-Yu↗
NASA NTRS2015

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

High temperature↗