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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

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NASA NTRS1988

A CMOS matrix for extracting MOSFET parameters before and after irradiation

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Blaes, B. R.↗

NASA NTRS1987

Propagation delay measurements from a timing sampler intended for use in space

A 3-micron CMOS timing sampler is described which is a test circuit designed into the Jet Propulsion Labs' CRRES chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches and decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 ns, with a resolution of 100 ps. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET threshold-voltage shifts and effective modal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-V-threshold shift, the pair delay increased from its preradiation value by 360 ps for a rising step input and decreased by 190 ps for a falling step input.

Blaes, B. R.↗

NASA NTRS1995

Radiation Evaluation of an Advanced 64Mb 3.3V DRAM and Insights into the Effects of Scaling on Radiation Hardness

In this paper, total ionizing dose radiation evaluations of the Micron 64 Mb 3.3 V, fast page mode DRAM and the IBM LUNA-ES 16 Mb DRAM are presented. The effects of scaling on total ionizing dose radiation hardness are studied utilizing test structures and a series of 16 Mb DRAMs with different feature sizes from the same manufacturing line. General agreement was found between the threshold voltage shifts of 16 Mb DRAM test structures and the threshold voltage measured on complete circuits using retention time measurements. Retention time measurement data from early radiation doses are shown that allow internal failure modes to be distinguished.

Radiation Hardness↗

NASA NTRS1991

CRRES microelectronic test chip

The JPL CRRES chip was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three orders of magnitude smaller than would be estimated from Co-60 ground tests. Unshielded (outer board) MOSFETs have a threshold-voltage damage factor that would be estimated from Co-60 ground tests. Temperature swings as large as 23 C with a 22.5 orbit periodicity affected the MOSFET data and were removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix, thus reducing the complexity and mass of the experiment.

Lin, Y.-S.↗

NASA NTRS1987

A study of charged particles/radiation damage to VLSI device materials

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Okyere, John G.↗

NASA NTRS2001

2D Quantum Transport Modeling in Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗

NASA NTRS2000

2D Quantum Mechanical Study of Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗

NASA NTRS2005

Single Particle Damage Events in Candidate Star Camera Sensors

Si charge coupled devices (CCDs) are currently the preeminent detector in star cameras as well as in the near ultraviolet (uv) to visible wavelength region for astronomical observations in space and in earth-observing space missions. Unfortunately, the performance of CCDs is permanently degraded by total ionizing dose (TID) and displacement damage effects. TID produces threshold voltage shifts on the CCD gates and displacement damage reduces the charge transfer efficiency (CTE), increases the dark current, produces dark current nonuniformities and creates random telegraph noise in individual pixels. In addition to these long term effects, cosmic ray and trapped proton transients also interfere with device operation on orbit. In the present paper, we investigate the dark current behavior of CCDs - in particular the formation and annealing of hot pixels. Such pixels degrade the ability of a CCD to perform science and also can present problems to the performance of star camera functions (especially if their numbers are not correctly anticipated). To date, most dark current radiation studies have been performed by irradiating the CCDs at room temperature but this can result in a significantly optimistic picture of the hot pixel count. We know from the Hubble Space Telescope (HST) that high dark current pixels (so-called hot pixels or hot spikes) accumulate as a function of time on orbit. For example, the HST Advanced Camera for Surveys/Wide Field Camera instrument performs monthly anneals despite the loss of observational time, in order to partially anneal the hot pixels. Note that the fact that significant reduction in hot pixel populations occurs for room temperature anneals is not presently understood since none of the commonly expected defects in Si (e.g. divacancy, E center, and A-center) anneal at such a low temperature. A HST Wide Field Camera 3 (WFC3) CCD manufactured by E2V was irradiated while operating at -83C and the dark current studied as a function of temperature while the CCD was warmed to a sequence of temperatures up to a maximum of +30C. The device was then cooled back down to -83 and re-measured. Hot pixel populations were tracked during the warm-up and cool-down. Hot pixel annealing began below 40C and the anneal process was largely completed before the detector reached +3OC. There was no apparent sharp temperature dependence in the annealing. Although a large fraction of the hot pixels fell below the threshold to be counted as a hot pixel, they nevertheless remained warmer than the remaining population. The details of the mechanism for the formation and annealing of hot pixels is not presently understood, but it appears likely that hot pixels are associated with displacement damage occurring in high electric field regions.

Marshall, Paul↗

NASA NTRS1975

Effects of ionizing radiation on CCD's

The effects of 1.2 MeV gamma radiation and 20 MeV electrons on the operational characteristics of CCDs are studied. The effects of ionizing radiation on the charge transfer efficiency, dark current, and input/output circuitry are described. The improved radiation hardness of buried channel CCDs is compared to surface channel results. Both ion implanted and epitaxial layer buried channel device results are included. The advantages of using a single thickness SiO2 gate dielectric are described. The threshold voltage shifts and surface state density changes of dry, steam, and HCl doped oxides are discussed. Recent results on the recovery times and total dose effects of high dose rate pulses of 20 MeV electrons are reported.

Hartsell, G. A.↗

NASA NTRS1984

Total-dose and dose-rate dependence of proton damage in MOS devices during and after irradiation

Rad-hard CMOS/bulk inverters with input gates high and low were irradiated by protons with a nominal energy of 8 MeV in an effort to determine the total-dose and dose-rate dependence of threshold voltage shifts, both during and immediately after irradiation and over extended periods of time thereafter. It is shown that the effects in rad-hard MOS devices which are produced by specific proton and electron energies in the space environment could be simulated by cobalt-60 induced effects through careful and proper selection of total does and dose rates. This selection must be based on an experimentally established relationship of Co-60 to electron or proton damage. It is demonstrated that the simulation can be accomplished both during and after irradiation, in the long-term postirradiation period, as well as in the damage state immediately after bombardment.

Stassinopoulos, E. G.↗

NASA NTRS1984

MOSFET and MOS capacitor responses to ionizing radiation

The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.

Benedetto, J. M.↗

NASA NTRS1986

Characterization of InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic In(y)Ga(1-y)As/Al0.15-Ga0.85As y = 0.05-0.2 MODFET's grown by MBE have been characterized at dc (300 and 77 K) and RF frequencies. Transconductances as high 310 and 380 mS/mm and drain currents as high as 290 and 310 mA/mm were obtained at 300 and 77 K, respectively, for 1-micron gate lengths and 3-micron source-drain spacing devices. Lack of persistent trapping effects, I-V collapse, and threshold voltage shifts observed with these devices are attributed to the use of low mole fraction Al(x)Ga(1-x)As while still maintaining two-dimensional electron gas concentrations of about 1.3 x to the 12th per sq cm. Detailed microwave S-parameter measurements indicate a current gain cut-off frequency of 24.5 GHz when y = 0.20, which is as much as 100 percent better than similar GaAs/AlGaAs MODFET structures, and a maximum frequency of oscillation of 40 GHz.

Ketterson, Andrew A.↗

NASA NTRS1992

CRRES microelectronic test chip orbital data. II

Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data.

Soli, G. A.↗

NASA NTRS1993

Evaluation of radiation effects in re-oxidized nitrided oxide devices by hot carrier stressing at 77 K

An attempt has been made to understand the mechanisms of radiation induced degradation by using different types of hot carrier (HC) stressing experiments. The degradation of re-oxidized nitrided oxide gate dielectric due to irradiation and hot carriers are reported. The effect of electron and hole traps of the virgin device on radiation induced threshold voltage shift is discussed.

Das, N. C.↗

NASA NTRS2000

Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub 100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study

In this paper we present a detailed simulation study of the influence of quantum mechanical effects in the inversion layer on random dopant induced threshold voltage fluctuations and lowering in sub 100 nm MOSFETs. The simulations have been performed using a 3-D implementation of the density gradient (DG) formalism incorporated in our established 3-D atomistic simulation approach. This results in a self-consistent 3-D quantum mechanical picture, which implies not only the vertical inversion layer quantisation but also the lateral confinement effects related to current filamentation in the 'valleys' of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical dopant fluctuations, is an increase in both threshold voltage fluctuations and lowering. At the same time, the random dopant induced threshold voltage lowering partially compensates for the quantum mechanical threshold voltage shift in aggressively scaled MOSFETs with ultrathin gate oxides.

Asenov, Asen↗

NASA NTRS2001

An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

Jackson, S. A.↗

NASA NTRS2001

Nano-Transistor Modeling: Two Dimensional Green's Function Method

Two quantum mechanical effects that impact the operation of nanoscale transistors are inversion layer energy quantization and ballistic transport. While the qualitative effects of these features are reasonably understood, a comprehensive study of device physics in two dimensions is lacking. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL (Drain Induced Barrier Lowering), and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI).

Svizhenko, Alexei↗

NASA NTRS2009

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Buchner, S.↗