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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (less than 250 V) 4H-SiC p(+)n Junction diodes: DC Properties - Part 1

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = 1c with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4)/sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (<250 V) 4H-SiC p+n Junction Diodes - Part 1: DC Properties

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = lc with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4) sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1978

FETSIM user's manual and example

A batch program written in FORTRAN IV which does D.C. and transient analysis of MOS circuits is presented. Circuits employing N-MOS transistors and/or P-MOS transistors in either a bulk technology or an SOS technology, or almost any combination of R-C elements may be analyzed. The program requires as input data the complete circuit topology, device parameters, process parameters, and control parameters. The user can specify initial node conditions and the input pulse format. For example, pulse rise time, fall time, width and time between succeeding pulses are all independently controllable. The program contains a sophisticated mathematical model that can accurately handle either NMOS, P-MOS, Bulk or SOS devices. Sensitivity to process changes is maintained by requiring such process parameters as threshold voltage and doping level as program inputs.

Source record↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗
NASA NTRS2000

Towards Evolving Electronic Circuits for Autonomous Space Applications

The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

Lohn, Jason D.↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

Lohn, Jason D.↗
NASA NTRS2019

Level Set Topology Optimization of Load Carrying Heat Dissipation Devices

In this paper, we introduce a level set method topology optimization method of structures subjected to coupled mechanical and thermal loads. Different examples considering compliance minimization and stress minimization under temperature and volume constraints, and mass minimization under stress and temperature constraints, are presented. The p-norm of the stress field and temperature field is used to approximate the maximum stress and temperature, respectively. The developed method is applied in the design of an L-bracket and a battery package. The results show that designs obtained by ignoring the thermal or structural constraints can result in high values of temperature or stress, respectively.

Kambampati, Sandilya↗
NASA NTRSDate not supplied

On the Moon to Stay: Challenges Presented to Power Electronics Technology by Sustained Operations on the Lunar Surface

NASA’s Artemis Program seeks not only to return humans to the Moon for the first time since the 1970’s but also to provide the technological basis for infrastructure that will enable permanent and expanding scientific and industrial exploitation of the Lunar surface. The primary purpose of this infrastructure is to generate and distribute power to a diverse and growing range of scientific and industrial assets, and the keys to success for this function are power management and control circuits that are highly reliable and maintainable for a decade of operation in the extreme thermal, radiation, and dust environment of the Lunar surface. While various combinations of wide band gap semiconductors, electronic devices, circuit topologies, and shielding schemes have been successfully developed for mission environments ranging from low Earth orbit to the Jovian system, power management technology has not been optimized to meet the full combination of mission requirements for the Lunar surface. To accomplish this, NASA requests the dedicated focus of the power electronics industry.

semiconductors↗
NASA NTRS1997

Laboratory Plasma Source as an MHD Model for Astrophysical Jets

The significance of the work described herein lies in the demonstration of Magnetized Coaxial Plasma Gun (MCG) devices like CPS-1 to produce energetic laboratory magneto-flows with embedded magnetic fields that can be used as a simulation tool to study flow interaction dynamic of jet flows, to demonstrate the magnetic acceleration and collimation of flows with primarily toroidal fields, and study cross field transport in turbulent accreting flows. Since plasma produced in MCG devices have magnetic topology and MHD flow regime similarity to stellar and extragalactic jets, we expect that careful investigation of these flows in the laboratory will reveal fundamental physical mechanisms influencing astrophysical flows. Discussion in the next section (sec.2) focuses on recent results describing collimation, leading flow surface interaction layers, and turbulent accretion. The primary objectives for a new three year effort would involve the development and deployment of novel electrostatic, magnetic, and visible plasma diagnostic techniques to measure plasma and flow parameters of the CPS-1 device in the flow chamber downstream of the plasma source to study, (1) mass ejection, morphology, and collimation and stability of energetic outflows, (2) the effects of external magnetization on collimation and stability, (3) the interaction of such flows with background neutral gas, the generation of visible emission in such interaction, and effect of neutral clouds on jet flow dynamics, and (4) the cross magnetic field transport of turbulent accreting flows. The applicability of existing laboratory plasma facilities to the study of stellar and extragalactic plasma should be exploited to elucidate underlying physical mechanisms that cannot be ascertained though astrophysical observation, and provide baseline to a wide variety of proposed models, MHD and otherwise. The work proposed herin represents a continued effort on a novel approach in relating laboratory experiments to astrophysical jet observation. There exists overwhelming similarity among these flows that has already produced some fascinating results and is expected to continue a high pay off in future flow similarity studies.

Mayo, Robert M.↗
NASA NTRS2003

The Development of Design Tools for Fault Tolerant Quantum Dot Cellular Automata Based Logic

We are developing software to explore the fault tolerance of quantum dot cellular automata gate architectures in the presence of manufacturing variations and device defects. The Topology Optimization Methodology using Applied Statistics (TOMAS) framework extends the capabilities of the A Quantum Interconnected Network Array Simulator (AQUINAS) by adding front-end and back-end software and creating an environment that integrates all of these components. The front-end tools establish all simulation parameters, configure the simulation system, automate the Monte Carlo generation of simulation files, and execute the simulation of these files. The back-end tools perform automated data parsing, statistical analysis and report generation.

Armstrong, Curtis D.↗
NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗
NASA NTRS2005

Evolvable hardware system at extreme low temperatures

This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hardening-by-process and hardening-by-design, 'hardening-by-reconfiguration ', when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive selfreconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. This paper demonstrates this technique for circuit evolution and recovery at liquid nitrogen temperatures (-196.6 (deg)C). In addition, preliminary tests are performed to assess the survivability limitations of the evolutionary processor at extreme low temperatures.

evolvable harware↗
NASA NTRS1991

MAX - An advanced parallel computer for space applications

MAX is a fault-tolerant multicomputer hardware and software architecture designed to meet the needs of NASA spacecraft systems. It consists of conventional computing modules (computers) connected via a dual network topology. One network is used to transfer data among the computers and between computers and I/O devices. This network's topology is arbitrary. The second network operates as a broadcast medium for operating system synchronization messages and supports the operating system's Byzantine resilience. A fully distributed operating system supports multitasking in an asynchronous event and data driven environment. A large grain dataflow paradigm is used to coordinate the multitasking and provide easy control of concurrency. It is the basis of the system's fault tolerance and allows both static and dynamical location of tasks. Redundant execution of tasks with software voting of results may be specified for critical tasks. The dataflow paradigm also supports simplified software design, test and maintenance. A unique feature is a method for reliably patching code in an executing dataflow application.

Lewis, Blair F.↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS1989

MCTs and IGBTs - A comparison of performance in power electronic circuits

There is a continuous demand for improvements in the quality of switching power devices, such as higher switching frequency, higher withstand voltage capability, larger current-handling capability, and lower conduction losses. However, for single-conduction-mechanism devices (SCRs, GTOs, BJTs, FETs), possessing all these features is probably unrealizable for physical reasons. An attractive solution appears to be double-mechanism devices, in which the features of both a minority carrier device (BJT or SCR) and a majority carrier device (MOSFET) are embedded. Both IGBTs (insulated-gate bipolar transistors) and MCTs (MOS-controlled thyristors) belong to this family of double-mechanism devices and promise to have a major impact on converter circuit signs. The authors deal with the major features of these two devices, pointing out those that are most critical to the design of converter topologies. In particular, the two devices have been tested both in a chopper and in two resonant link converter topologies, and the experimental results are reported.

Sul, S. K.↗
NASA NTRS1978

C-MOS array design techniques

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Feller, A.↗
NASA NTRSDate not supplied

Modeling and Simulation Efforts to Support Improved Comfort in ARGOS

BACKGROUND: The Active Response Gravity Offload System (ARGOS) provides an analog environment for extravehicular activity (EVA) testing and training. Discomfort has been observed during longer suited test sessions. While the subject’s core is offloaded during surface EVA evaluations, his/her arms experience full Earth gravity and can become overly fatigued, especially during suited tests which involve reaching and prolonged arm extensions. A device (ARGOS Negation of Gravitational Effects on the Limbs: ANGEL) to offload the weight of the arms and suit sleeves is being developed by JSC’s Flight Systems Branch, and here we present preliminary modeling of that device using the open-source biomechanical tool OpenSim [1,2] with an in-house developed plugin. We analyze a series of motions performed by a single shirt-sleeved subject with goals of characterizing the device, validating the model, and predicting whether reduced gravity conditions (i.e., lunar gravity (Lg) or Martian gravity (Mg)) can be accurately simulated with the device, as well as providing comfort to the ARGOS user. METHODS AND RESULTS: To model the offload device, we augment the OpenSim human model topology with the offload mechanism components and joints, using CAD models to represent the mechanism graphically. The joint angles of the device are either obtained from (1) inverse kinematics (IK) using motion capture markers on the various components of the device or (2) calculated in the OpenSim plugin by modeling how the components configure themselves under the offloading spring tension given a particular IK-derived arm position. Given the joint angles of the device, the resulting force on the arm is computed by the plugin and applied as an external load in inverse dynamics (ID) in order to enable study of overall shoulder joint torques as well as offload achieved. We verify the calculated joint angles by using the inverse kinematic data and the forces from manual measurements of the spring both independently and integrated within the device. We found that calculated joint angles generally represent the angles measured and computed with IK, supporting a possible analysis workflow inputting human motion data and observing system behavior under varied design parameters. In two different device configurations in which the maximum applied force was 131 N, our current model accurately captured force with a difference of 2-3 N from measured loads. Though our initial test was performed with a shirt-sleeve subject, arm weights were added to emulate the weight of the suit sleeve and the subject was positioned in a test stand with a Mark-III Hard Upper Torso (HUT) and Portable Life Support System (PLSS) mockup. Arm range of motion tasks were performed outside of the HUT, inside the HUT, and inside the HUT while using the device. A variety of other upper body tasks were completed as well. In summary, we have developed a model to investigate and verify an upper limb offload device currently in development. We believe this model will be a valuable tool not only for device characterization but also to predict proper configurations to simulate Lg or Mg conditions, investigate range of motion concerns, predict limitations such as internal collisions and contacts, and inform future design improvements.

L B Nilsson↗