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DC Link Voltage Balancing of the Active Front-End for the Extreme Fast Charging Stations
One of the most important challenges of the extreme fast charging (XFC) stations is to balance the DC link voltages of the active front-end (AFE). The multilevel cascaded H-bridge (CHB) converter is a great topology for the AFE applications due to the high power density, low total harmonic distortion (THD), and a low number of active and passive components. In this paper, a technique is proposed for balancing DC-link capacitor voltages of a three-phase CHB converter, when a phase shiftPWM modulation technique is used on all cells of the converter. To reach this goal, the redundant states of the CHB converters are used for generating different AC voltage levels by sorting the voltages of the converters. The proposed voltage balancing technique uses the principles that are employed for the DC link voltage balancing of the low-frequency modulation techniques to balance the DC link voltages of the CHB converter. As shown in this paper, the DC link voltages of the CHB converter can accurately be balanced very fast without using PI controllers, which are used in the conventional DC link voltage balancing techniques. A controller also is proposed which will be used to control the dq currents of the CHB converter. To verify the advantages of the proposed technique, the simulation results of the proposed technique will be carried out in a three-phase 7-cell CHB AFE.
A Novel Voltage Balancing Control With dv/dt Reduction for 10-kV SiC MOSFET-Based Medium Voltage Modular Multilevel Converter
Using high voltage (HV) silicon carbide (SiC) power semiconductors in a modular multilevel converter (MMC) is promising because it results in fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulsewidth modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of the single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this article, limiting the maximum dv/dt to the dv/dt of a single power semiconductor and also maintaining the voltage balance performance. Furthermore, the proposed voltage balancing control is experimentally validated in a 10-kV SiC mosfet based MMC with four submodules per arm.
Stacked Low-Inertia Converter or Solid-State Transformer: Modeling and Model Predictive Priority-Shifting Control for Voltage Balance
This paper presents control challenges of stacked low-inertia converter (SLIC) or cascaded reduced dc-link solid-state transformer (SST) and proposes a novel model predictive priority-shifting (MPPS) control with implicit modulator and a discrete-time large-signal model for voltage balancing and dc-link regulation. Low-inertia converters, featuring small electrolytic capacitor-less dc links, dramatically reduce cost, size, and weight compared to conventional solutions. However, without a large dc-link buffer, the input and output are tightly coupled, leading to significant control challenges. The control becomes even more challenging with these converters stacked input-series output-parallel (ISOP) for medium-voltage (MV) grid, which causes coupling between the modules besides the coupling within each module. This paper analyzes the multi-objective, multi-degree of freedom control problem, using the modular soft-switching solid-state transformer (M-S4T) as an example of the SLIC. First, distribution of control efforts under controller saturation is critical because multiple control objectives can be conflicting, especially when the module voltages are unbalanced and are being restored. The MPPS can shift the priorities to address this issue. Second, due to the low inertia and high dc-link ripple, classic space vector pulse-width modulation (SVPWM), average model with small-ripple assumption, and control design based on small-signal model cannot accurately modulate, model, and control the nonlinear reduced dc link. Therefore, a discrete-time large-signal model of the M-S4T is established to derive the predictive control in the MPPS. The MPPS and the PI control are compared in MV simulations to show the issue of applying the PI to the SLIC and the effectiveness of the MPPS for voltage balancing and dc-link regulation in a deadbeat manner. Finally, the proposed control is tested on a 5 kV ISOP SiC SST prototype to verify priority shifting to address controller saturation issue and fast and robust voltage balancing.
Inverter Controls for Smooth Transition Operation and Voltage Balancing of Networked Microgrids
With increasing penetrations of distributed energy resources (DERs), researchers have extensively studied the formation and networking of microgrids to improve reliability during distribution system outages. However, these operations might require DERs in the microgrids to switch between grid-following (GFL) and grid-forming (GFM) modes of operation. A smooth transition between the operation modes should be ensured to have a stable system operation and to avoid nuisance tripping. Additionally, as we network microgrids, inverter control schemes with voltage-balancing controls are needed for unbalanced distribution networks. This paper presents the design of a GFM and GFL capable inverter control scheme for reliable operation in networked microgrids with mechanisms for 1) smooth transition between the GFL and GFM modes, and 2) negative sequence voltage control for voltage balancing. Using electromagnetic transient (EMT) simulations, the control scheme is first tested on a simple two-source power system using a digital real-time simulator. Next, a real-world distribution feeder with unbalanced loading and multiple DERs is used to demonstrate stable operation during the networking of microgrids with voltage balance support.
Per-Phase Control for CHB Converters with Negative-Sequence Current and DC Voltage Balancing Control
This paper presents a per-phase controller for a grid-connected Cascaded H-Bridge (CHB) converter featuring negative sequence current regulation and DC bus voltage balancing capabilities. Unlike conventional three-phase controllers, each phase of the CHB can be separately and controlled to regulate the DC voltage and reactive power flow. per-phase negative sequence current control strategy is incorporated into the proposed controller to ensure compliance with IEEE Standard 2800-2022, which requires the absorption of negative-sequence reactive current during grid voltage disturbances. Furthermore, a feed-forward control-based DC bus voltage balancing method is employed, which eliminates the need for the integrator commonly used in traditional approaches. The performance of the proposed controller is validated under various unbalanced grid scenarios and DC bus voltage imbalances through electromagnetic transient (EMT) simulation using a three-phase, three-level grid-connected CHB–Dual Active Bridge (DAB) converter testbed developed on MATLAB/Simulink. Additionally, the performance of the negative-sequence current regulation is investigated through simulation under different unbalanced grid voltage scenarios.
Balancibility: Existence and uniqueness of power flow solutions under voltage balance requirements
Not Available
A Six-Phase Space Vector PWM Technique for Wide Bandgap Device-Based Three-Level Inverters
This article presents a space vector pulsewidth modulation (SVPWM) technique for wide bandgap (WBG) device-based three-level (3L) six-phase inverters. Implementation of the SVPWM techniques for any six-phase inverter is complex for its high number of possible voltage vectors. Different six-phase load configurations are also possible depending on the angle between two consecutive phases and neutral point connections. The implementation techniques change depending on the load configuration. Moreover, a common neutral point for all six phases leads to circulating currents. Capacitor voltage balancing is also needed for 3L inverters. Capacitor voltage balancing and addressing the circulating current problem further increases the implementation complexity. In this article, a generalized SVPWM technique is proposed for the six-phase 3L inverters that is implementable using two three-phase 3L SVPWM blocks. The SVPWM technique also ensures dc bus capacitor voltage balancing and minimizes circulating current. Here, the SVPWM technique is experimentally verified using a GaN-based 3L six-phase active neutral point clamped (ANPC) inverter prototype, and the results are presented in this article.
Modeling and Control of Cascaded Bridgeless Multilevel Rectifier Under Unbalanced Load Conditions
The goal of this project is to model and control a novel unidirectional cascaded multilevel bridgeless rectifier as an active front end in medium and high voltage applications. This topology has many advantages over a conventional cascaded H-bridge rectifier, such as lower implementation cost, higher reliability, and greater flexibility with similar power quality.The steady-state mathematical model is used to develop a method for the voltage balancing of dc cells. Power factor analysis is discussed to achieve unity power factor using fully controlled hbridge cells. Power loss, efficiency, and cost comparison studies between the traditional cascaded H-Bridge converter and the proposed bridgeless converter demonstrate the advantages. A novel control strategy is proposed to achieve dc voltage balancing, fast and robust grid synchronization and power factor correction under unbalanced load conditions. Simulation and experimental results validate the models and control method.
A Single Passive Gate-Driver for Series Connected Power Devices in DC Circuit Breaker Applications
This letter proposes a novel single passive gate driver solution based on passive devices to control series-connected power semiconductor devices for dc circuit breaker (DCCB) applications. The transient suppression devices (e.g., metal oxide varistors) are utilized to achieve natural voltage balancing among the series devices, while providing the discharge path of the gate capacitor of the upper devices. Here, the proposed method is very simple, cost effective and more compact compared with conventional voltage balancing method-based DCCBs. Besides, gate voltage oscillation during the voltage recovery process is mitigated by the addition of an extra gate capacitor. Simulation and experimental results are provided to verify the effectiveness of proposed method.
Duty-Cycle Predictive Control of Quasi-Z-Source Modular Cascaded Converter Based Photovoltaic Power System
A duty-cycle predictive control is proposed for dc grid integration of front-end isolated quasi-Z-source modular cascaded converter (qZS-MCC) photovoltaic (PV) power system. The post-stage qZS half-bridge dc-dc converter deals with PV maximum power point tracking, dc grid integration, and dc-link voltage balance; whereas, the front-end isolation converters operate at a constant duty cycle of 50%. Thus, it saves control hardware resources while overcoming challenges from PV-panel voltage variations and dc-bus voltage limit. The proposed control uses the derived circuit model to predict the global active-state duty cycle for grid-connected current control and predict the shoot-through duty cycles for dc-link voltage balance, achieving a fast and accurate tracking target. The proposed control method has advantages of: i) eliminating weighting factors that exist in conventional model predictive control (MPC), ii) no sophisticated loop parameters design that exists in proportional-integral (PI) control, iii) operating at constant switching frequency that is different from the conventional MPC with variable switching frequency. Simulation and experimental tests are carried out to verify the effectiveness of the proposed control method and compare with the PI-based control system.
Modeling and control of cascaded bridgeless multilevel rectifier under unbalanced load conditions
The goal of this project is to model and control a novel unidirectional cascaded multilevel bridgeless rectifier as an active front end in medium and high voltage applications. This topology has many advantages over a conventional cascaded H-bridge rectifier, such as lower implementation cost, higher reliability, and greater flexibility with similar power quality. The complete design process of the proposed converter is developed step by step in order to meet all the desired objectives. The steady-state mathematical model is used to develop a method for the voltage balancing of dc cells. Power factor analysis is discussed to mathematically derive requirements for the number of partially controlled and fully controlled H-bridges in the proposed H-bridge converter. Power loss, efficiency, and cost comparison studies between the traditional cascaded H-Bridge converter and the proposed bridgeless converter demonstrate the advantages. After exploring various well-established control methods, a novel control strategy is proposed to achieve dc voltage balancing, fast and robust grid synchronization, power factor correction, and elimination of zero crossing current distortion under both balanced and unbalanced load conditions. The converter can also be used for reactive power compensation in a grid tied power system if a sufficient number of fully controlled H-bridge modules are included. Processor-In-the-Loop (PIL) simulation has been the utilized to validate the performance of discrete control structure. Simulation and experimental results validate the models and control method.