Engineering topics
Publications and source records attributed to Daud, Taher.
Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.
High-speed, analog, fully-parallel, and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation intensive feature classification application was demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as an application specific coprocessor for solving real world problems at extremely high data rates.
Proposed array of programmable synaptic connections for electronic neural network applications offers multiple quantized levels of connection strength using only simple, two-terminal, binary microswitch devices. Subgrids in fine grid of programmable resistive connections connected externally in parallel to form coarser synaptic grid. By selection of pattern of connections in each subgrid, connection strength of synaptic node represented by that subgrid set at quantized "gray level". Device structures promise implementations of quantized-"gray-scale" synaptic arrays with very high density.
Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.
A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix. Each memory matrix comprises, a first layer comprising a plurality of electrically separated row conductors; a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; and, a plurality of resistance elements electrically connected between the row condutors and the column conductors at respective intersections of the row conductors and the column conductors, each resistance element comprising, in series, a first resistor of sufficiently high ohmage to conduct a sensible element current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross, the second resistor having the quality of breaking down to create a short therethrough upon the application of a breakdown level voltage across the first and second resistors.
A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.
Photovoltaic device senses hydrogen developed to test degradation of diodes with platinum flash gates on backs. Sensing element is p/n junction rather than conventional Schottky barrier or metal oxide/silicon field-effect transistor. Hydrogen-indicating electrical signal modulated optically rather than electrically. Layered structure of hydrogen detector and principle of operation resemble silicon solar photovoltaic cell. Hydrogen detector responds to hydrogen in atmosphere within minutes and recovers quickly when hydrogen removed.
New process excludes usual silicon oxide passivation. Changes in principal electrical parameters during two kinds of processing suggest antireflection treatment almost as effective as oxide treatment in passivating cells. Does so without disadvantages of SiOx passivation.
Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.
The introduction of the flash gate has made possible the fabrication of backside-illuminated CCDs with high sensitivity and stability throughout a wide range of ultraviolet and visible wavelengths (100 to 5000 A). It had been determined previously that the characteristics of the oxide layer beneath the gate are critical to the ultimate achievable CCD performance. However, by creating an improved oxide layer in conjunction with the flash gate, it is now possible to consistently produce CCDs with near-ideal UV performance. In this paper recent results and related background theory that optimize the flash gate specifically for application in the UV are presented.
Recent developments of backside treatment for the backside-illuminated scientifc CCD imagers have shown near-theoretical efficiency even at the short wavelength region of the spectrum. By using SEM performance comparisons of backside-treated and untreated CCDs to an electron flux varying from 1 to 100 pA and beam energy ranging from less than 1 keV up to 20 keV are obtained. The theoretical analysis, the SEM testing procedure, and the quantum efficiency measurement results are presented. It is shown, for example, that the average quantum efficiency increases from less than 1 percent for an untreated CCD to nearly 40 percent for a backside-treated CCD at a beam energy of 1 kev.
A multijunction silicon solar cell of high efficiency is provided by providing a tunnel junction between the solar cell junctions to connect them in series. The tunnel junction is comprised of p+ and n+ layers of high band gap 3-5 or 2-6 semiconductor materials that match the lattice structure of silicon, such as GaP (band gap 2.24 eV) or ZnS (band gap 3.6 eV). Each of which has a perfect lattice match with silicon to avoid defects normally associated with lattice mismatch.
This paper presents, for the first time, a detailed sensitivity analysis of key cell parameters on silicon-cell efficiency by incorporating advanced solar cell physics in a sophisticated numerical simulation program. It delineates the true physical barriers to obtaining a high-efficiency silicon solar cell. Specific parameters presently limiting cell efficiency are identified to be the minority carrier lifetime and the recombination velocities at the front and back surfaces. Practical cell efficiencies in the vicinity of 22 percent are estimated to be attainable by using good quality silicon crystal and substantially reducing surface recombination velocities.
A method for growing a high purity, low defect layer of semiconductor is described. This method involves depositing a patterned mask of a material impervious to impurities of the semiconductor on a surface of a blank. When a layer of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings in the mask and will bridge the connecting portions of the mask to form a continuous layer having improved purity, since only the portions overlying the openings are exposed to defects and impurities. The process can be iterated and the mask translated to further improve the quality of grown layers.
A theoretical model is presented which predicts the output response of a CCD to soft X-ray spectra. The model simulates the four fundamental parameters that ultimately limit CCD performance: quantum efficiency, charge collection efficiency, charge transfer efficiency, and read noise. Simulated results are presented for a wide variety of CCD structures, and general conclusions are presented about achieving a practical balance of sensitivity, energy, and spatial resolution for an AXAF instrument. The results of the analysis are compared to an existing state-of-the art CCD and improvements which will be made in the near future are projected.
Preliminary findings are presented for a new approach that significantly improves the quantum efficiency of the current generation of high-performance, thinned, backside illuminated silicon CCDs. Experiments have shown that the application of a less than 4-micron thick layer of metal with high work function to the backside of the CCD can yield 100-percent internal quantum efficiency in the visible, UV, XUV and soft X-ray regions of the spectrum. Theory and solid state models describing the new technique (the 'CCD flash gate'), and a considerable amount of experimental data, are discussed. Specific recommendations for use of the flash gate in present and future CCDs are also reviewed.