NASA Electronic Parts & Packaging (NEPP) program: contributions to MER success
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Engineering topics
Publications and source records attributed to Ghaffarian, R..
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For high reliability applications, visual inspection has been the key technique for most conventional electronic package assemblies. Now, the use of x-ray technique has become an additional inspection requirement for quality control and detection of unique defects due to manufacturing of advanced electronic array packages such as ball grid array (BGAs) and chip scale packages (CSPs).
This paper discusses limitation of each system and provides representative inspection images for CCGA/BGA assemblies.
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Inspection results along with SEM and optical cross-sectional photos revealing damage and failure mechanisms will also be presented.
The test results for numerous chip scale package assembly performed under MicrotypeBGA Consortium led by the Jet Propulsion Laboratory have been published previously.
This paper reports the results of an experiment that utilized the JPL's area array consortium test vehicle design, containing a myriad of mixed technology components with an OSP finish. The details of the reliability study are presented in this paper.
System in a package (SIP) development is a response to an increasing demand for integration of different functions into one unit to reduce size and cost and improve functionality. Qualification of the newly developed multifunctional electronics are becoming complex at the package level and even more at the second and system levels.
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Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
A comparison of the data from microaccelerometers of the same type and between several types will be presented. Self-test output signals and X-ray evaluation test data after completion of 182 thermal cycles will also be presented.
A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.
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The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.
A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
This paper reviews the current status of IC and MEMS packaging technology with emphasis on reliability, compares the norm for IC packaging reliability evaluation and identifies challenges for development of reliability methodologies for MEMS, and finally, proposes the use of COTS MEMS in order to start generating statistically meaningful reliability data as a vehicle for future standardization of reliability test methodology for MEMS packaging.