Engineering topics

Ho, Fat Duen

Publications and source records attributed to Ho, Fat Duen.

14 records

NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗

NASA NTRS2006

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

MacLeod, Todd, C.↗

NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗

NASA NTRS2004

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Phillips, Thomas A.↗

NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗

NASA NTRS2002

Simulation Model of A Ferroelectric Field Effect Transistor

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

MacLeod, Todd C.↗

NASA NTRS2001

Electronic Model of a Ferroelectric Field Effect Transistor

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

MacLeod, Todd C.↗

NASA NTRS1999

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

MacLeod, Todd C.↗

NASA NTRS1999

I-V Characteristics of a Ferroelectric Field Effect Transistor

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

MacLeod, Todd C.↗

NASA NTRS1996

Studies of Large-Area Inversion-Layer Metal-Insulator-Semiconductor (IL/MIS) Solar Cells and Arrays

Many inversion-layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. There are around eighteen 1 cm(exp 2) IL/MIS solar cells which have efficiencies greater than 7%. There are only about three 19 cm(exp 2) IL/MIS cells which have efficiencies greater than 4%. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved. A lot of effort and progress have been made in this area. A comprehensive model for MIS contacts under dark conditions has been developed that covers a wide range of parameters. It has been applied to MIS solar cells. One of the main advantages of these models is the prediction of the range of the thin oxide thickness versus the maximum efficiencies of the MIS solar cells. This is particularly important when the thickness is increased to 25 A. This study is very useful for our investigation of the IL/MIS solar cells. The two-dimensional numerical model for the IL/MIS solar cells has been tried to develop and the results are presented in this report.

Ho, Fat Duen↗

NASA NTRS1992

Further study of inversion layer MIS solar cells

Many inversion layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. As of today, the best cell fabricated by us has a 9.138 percent AMO efficiency, with FF = 0.641, V(sub OC) = 0.557 V, and I(sub SC) = 26.9 micro A. Efforts made for fabricating an IL/MOS solar cell with reasonable efficiencies are reported. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved by using two different process methods. Comparison of these two different thin oxide processings is reported. The effects of annealing time of the sample are discussed. The range of the resistivity of the substrates used in the IL cell fabrication is experimentally estimated. Theoretical study of the MIS contacts under dark conditions is addressed.

Ho, Fat Duen↗

NASA NTRS1991

Computer modeling of inversion layer MOS solar cells and arrays

A two dimensional numerical model of the inversion layer metal insulator semiconductor (IL/MIS) solar cell is proposed by using the finite element method. The two-dimensional current flow in the device is taken into account in this model. The electrostatic potential distribution, the electron concentration distribution, and the hole concentration distribution for different terminal voltages are simulated. The results of simple calculation are presented. The existing problems for this model are addressed. Future work is proposed. The MIS structures are studied and some of the results are reported.

Ho, Fat Duen↗

NASA NTRS1987

Further study of inversion layer MOS solar cells

A group of inversion layer MOS solar cells has been fabricated. The highest value of open-circuit voltage obtained for the cells is 0.568V. One of the cells has produced a short-circuit current of 79.6 mA and an open-circuit voltage of 0.54V. It is estimated that the actual area AMO efficiency of this cell is 6.6 percent with an assumed value of 0.75 for its fill factor. Efforts made for fabricating an IL/MOS cell with reasonable efficiencies are reported. Future work for 4 sq cm IL cells and 25 sq cm IL cells is discussed.

Ho, Fat Duen↗

NASA NTRS1986

Inversion layer MOS solar cells

Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.

Ho, Fat Duen↗