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Lieneweg, Udo

Publications and source records attributed to Lieneweg, Udo.

At least 19 records

Toroidal-Core Microinductors Biased by Permanent Magnets

The designs of microscopic toroidal-core inductors in integrated circuits of DC-to-DC voltage converters would be modified, according to a proposal, by filling the gaps in the cores with permanent magnets that would apply bias fluxes (see figure). The magnitudes and polarities of the bias fluxes would be tailored to counteract the DC fluxes generated by the DC components of the currents in the inductor windings, such that it would be possible to either reduce the sizes of the cores or increase the AC components of the currents in the cores without incurring adverse effects. Reducing the sizes of the cores could save significant amounts of space on integrated circuits because relative to other integrated-circuit components, microinductors occupy large areas - of the order of a square millimeter each. An important consideration in the design of such an inductor is preventing magnetic saturation of the core at current levels up to the maximum anticipated operating current. The requirement to prevent saturation, as well as other requirements and constraints upon the design of the core are expressed by several equations based on the traditional magnetic-circuit approximation. The equations involve the core and gap dimensions and the magnetic-property parameters of the core and magnet materials. The equations show that, other things remaining equal, as the maximum current is increased, one must increase the size of the core to prevent the flux density from rising to the saturation level. By using a permanent bias flux to oppose the flux generated by the DC component of the current, one would reduce the net DC component of flux in the core, making it possible to reduce the core size needed to prevent the total flux density (sum of DC and AC components) from rising to the saturation level. Alternatively, one could take advantage of the reduction of the net DC component of flux by increasing the allowable AC component of flux and the corresponding AC component of current. In either case, permanent-magnet material and the slant (if any) and thickness of the gap must be chosen according to the equations to obtain the required bias flux. In modifying the design of the inductor, one must ensure that the inductance is not altered. The simplest way to preserve the original value of inductance would be to leave the gap dimensions unchanged and fill the gap with a permanent- magnet material that, fortuitously, would produce just the required bias flux. A more generally applicable alternative would be to partly fill either the original gap or a slightly enlarged gap with a suitable permanent-magnet material (thereby leaving a small residual gap) so that the reluctance of the resulting magnetic circuit would yield the desired inductance.

Lieneweg, Udo

Particle sensor array

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Buehler, Martin G.

Computing Misalignments From Measured Contact Resistances

Misalignments of contacts in integrated circuits computed, and measured contact resistances corrected for effects of misalignments by use of method based on relatively simple mathematical model of measured contact resistance. Flange resistance of aligned contact multiplied by semiempirical factor. Method particularly useful in estimating effects of misalignments on four- and six-terminal (Kelvin-tap) contact-resistance measurements taken with L-shaped test structures.

Lieneweg, Udo

Planar varactor frequency multiplier devices with blocking barrier

The invention relates to planar varactor frequency multiplier devices with a heterojunction blocking barrier for near millimeter wave radiation of moderate power from a fundamental input wave. The space charge limitation of the submillimeter frequency multiplier devices of the BIN(sup +) type is overcome by a diode structure comprising an n(sup +) doped layer of semiconductor material functioning as a low resistance back contact, a layer of semiconductor material with n-type doping functioning as a drift region grown on the back contact layer, a delta doping sheet forming a positive charge at the interface of the drift region layer with a barrier layer, and a surface metal contact. The layers thus formed on an n(sup +) doped layer may be divided into two isolated back-to-back BNN(sup +) diodes by separately depositing two surface metal contacts. By repeating the sequence of the drift region layer and the barrier layer with the delta doping sheet at the interfaces between the drift and barrier layers, a plurality of stacked diodes is formed. The novelty of the invention resides in providing n-type semiconductor material for the drift region in a GaAs/AlGaAs structure, and in stacking a plurality of such BNN(sup +) diodes stacked for greater output power with and connected back-to-back with the n(sup +) GaAs layer as an internal back contact and separate metal contact over an AlGaAs barrier layer on top of each stack.

Lieneweg, Udo

SRAM As An Array Of Energetic-Ion Detectors

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Buehler, Martin G.

Single Event Upset Behavior of CMOS Static RAM Cells

An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

Lieneweg, Udo

Barrier/n/n+ Varactor Frequency Multipliers

Barrier/n/n+ (BNN+) varactor diodes developed as frequency multipliers at millimeter and submillimeter wavelengths. Devices required to serve as frequency triplers or quintuplers to provide powers of order of milliwatts at frequencies from 0.1 THz to about 1 THz. Feature Mott or heterojunction barriers and back-to-back diode configuration, which make it possible to obtain symmetrical capacitance-versus-voltage characteristics with high ratio between maximum and minimum capacitances. Extension of barrier/intrinsic/n+ (BIN+) concept described in "BIN Diode for Submillimeter Wavelengths" (NPO-17258).

Lieneweg, Udo

Modeling of planar varactor frequency multiplier devices with blocking barriers

Models for optimization of planar frequency triplers with symmetrical C-V curves are presented. Role and limitation of various blocking barriers (oxide, Mott, heterojunction) are discussed. Devices with undoped drift regions (BIN) have moderate efficiency but a broad range of power operation, whereas devices with doped drift regions (BNN) have high efficiency in a narrow power window. In particular, an upper power limit of the BNN is caused by electron velocity saturation. Implementations in SiO2/Si and AlAs/GaAs and means for increasing the power of BNN structures are considered.

Lieneweg, Udo

Cross-Quint-Bridge Resistor

Integrated-circuit conductive test pattern intended to provide data on effects of design widths and design spacings upon actual widths of conductive lines. Provides for electrical measurements both on lines of unknown width and on features having known dimensions. Data from measurements on five bridges used to determine four parameters of mathematical model describing system. In principle, pattern determines effects of width and spacing and interaction between them.

Hannaman, David J.

Flange Correction For Metal-To-Metal Contacts

Improved mathematical model provides correction for flange effect in estimating resistance of square contact between two metal layers from standard four-terminal measurements. Extended version of one developed previously for contact between metal layer and semiconductor layer, wherein flange effect important in semiconductor layer only. Here flange effect in both metal layers significant. Interfacial resistances extracted more accurately.

Lieneweg, Udo

Comparison between analytical models and finite-difference simulations in transmission-line tap resistors and L-type cross-Kelvin resistors

Approximate analytical models of the transmission-line tap resistor and the cross-Kelvin resistor are compared with computer-simulated pseudo-three-dimensional resistor network models. The analytical formulas are in good agreement with the simulations over a useful range of parameters and are readily applied to the extraction of the contact resistivity and the sheet resistances of the semiconducting layer under and outside the contacts. The extraction procedure, which is easily implemented on a personal computer, is carried out for the case of alloyed AuGeNi/GaAs contacts, illustrating the importance of (1) distinguishing between layer sheet resistance under and outside the contacts and (2) considering two-dimensional current flow in the semiconducting layer.

Scorzoni, Andrea

Chain Of Test Contacts For Integrated Circuits

Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

Lieneweg, Udo

Formula Gives Better Contact-Resistance Values

Lateral currents in contact strips taken into account. Four-terminal test structures added to intergrated circuits to enable measurement of interfacial resistivities of contacts between thin conducting layers. Thin-film model simplified quasi-two-dimensional potential model that accounts adequately for complicated three-dimensional, nonuniform current densitites. Effects of nonuniformity caused by lateral current flow in strips summarized in equivalent resistance Rs and voltage Vs.

Lieneweg, Udo

Cross-contact chain

A system is provided for use with wafers that include multiple integrated circuits that include two conductive layers in contact at multiple interfaces. Contact chains are formed beside the integrated circuits, each contact chain formed of the same two layers as the circuits, in the form of conductive segments alternating between the upper and lower layers and with the ends of the segments connected in series through interfaces. A current source passes a current through the series-connected segments, by way of a pair of current tabs connected to opposite ends of the series of segments. While the current flows, voltage measurements are taken between each of a plurality of pairs of voltage tabs, the two tabs of each pair connected to opposite ends of an interface that lies along the series-connected segments. A plot of interface conductances on a normal probability chart, enables prediction of the yield of good integrated circuits from the wafer.

Lieneweg, Udo

Experiences in extraction of contact parameters from process-evaluation test-structures

Six-terminal-contact test structures are introduced for characterizing ohmic contacts between a metal and a heavily doped semiconductor layer. Specifically, the six-terminal test structure supplies the additional information needed in order to calculate the transmission length and eventual corrections to the characteristic resistance per unit width due to finite contact length. The essential feature of this test structure is a square contact with four taps in the lower (semiconductor) layer. Every other one of these taps is used for current injection ('front'). From the voltage drop at the opposite tap and the side taps, the 'end' resistance and the 'side' resistances are calculated. The test structures are shown to give valuable information complementary to the common front resistance measurements. The interfacial resistivity is obtained directly after proper correction for flange effects.

Lieneweg, Udo