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Ramesham, Rajeshuni

Publications and source records attributed to Ramesham, Rajeshuni.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Reliability of Sn/Pb and Lead-Free (SnAgCu) Solders of Surface Mounted Miniaturized Passive Components for Extreme Temperature (-185 C to +125 C) Space Missions

Surface mount electronic package test boards have been assembled using tin/lead (Sn/Pb) and lead-free (Pb-free or SnAgCu or SAC305) solders. The soldered surface mount packages include ball grid arrays (BGA), flat packs, various sizes of passive chip components, etc. They have been optically inspected after assembly and subsequently subjected to extreme temperature thermal cycling to assess their reliability or future deep space, long-term, extreme temperature environmental missions. In this study, the employed temperature range (-185oC to +125oC) covers military specifications (-55oC to +100oC), extreme old Martian (-120oC to +115oC), asteroid Nereus (-180oC to +25oC) and JUNO (-150oC to +120oC) environments. The boards were inspected at room temperature and at various intervals as a function of extreme temperature thermal cycling and bake duration. Electrical resistance measurements made at room temperature are reported and the tests to date have shown some change in resistance as a function of extreme temperature thermal cycling and some showed increase in resistance. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work will be carried out to understand the reliability of packages under extreme temperature applications (-185oC to +125oC) via continuously monitoring the daisy chain resistance for BGA, Flat-packs, lead less chip packages, etc. This paper will describe the experimental reliability results of miniaturized passive components (01005, 0201, 0402, 0603, 0805, and 1206) assembled using surface mounting processes with tin-lead and lead-free solder alloys under extreme temperature environments.

extreme temperatures,↗
NASA NTRS2011

Qualification of Bonding Process of Temperature Sensors to Extreme Temperature Deep Space Missions

A process has been explored based on the state-of-the-art technology to bond the platinum resistance thermometer (PRT) on to potential aerospace material such as a flat aluminum surface and a flexible copper tube to simulate coaxial cable for the flight applications. Primarily, PRTs were inserted into a metal plated copper braid to avoid stresses on the sensor while attaching the sensor with braid to the base material for long duration deep space missions. Appropriate pretreatment has been implemented in this study to enhance the adhesion of the PRTs to the base material. NuSil product has been chosen in this research to attach PRT to the base materials. The resistance (approx.1.1 k(Omega)) of PRTs has been electrically monitored continuously during the qualification thermal cycling testing from -150 C to +120 C and -100 C to -35 C. The test hardware has been thermal cycled three times the mission life per JPL design principles for JUNO project. No PRT failures were observed during and after the PRT thermal cycling qualification test for extreme temperature environments. However, there were some failures associated with staking of the PRT pig tails as a result of thermal cycling qualification test.

Extreme temperatures↗
NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗
NASA NTRS2010

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

PRTs↗
NASA NTRS2009

Use of Cumulative Degradation Factor Prediction and Life Test Result of the Thruster Gimbal Assembly Actuator for the Dawn Flight Project

The Dawn Ion Propulsion System is the ninth project in NASA s Discovery Program. The Dawn spacecraft is being developed to enable the scientific investigation of the two heaviest main-belt asteroids, Vesta and Ceres. Dawn is the first mission to orbit two extraterrestrial bodies, and the first to orbit a main-belt asteroid. The mission is enabled by the onboard Ion Propulsion System (IPS) to provide the post-launch delta-V. The three Ion Engines of the IPS are mounted on Thruster Gimbal Assembly (TGA), with only one engine operating at a time for this 10-year mission. The three TGAs weigh 14.6 kg.

Lo, C. John↗
NASA NTRS2008

Qualification Testing of Engineering Camera and Platinum Resistance Thermometer (PRT) Sensors for Mars Science Laboratory (MSL) Project under Extreme Temperatures to Assess Reliability and to Enhance Mission Assurance

Package Qualification and Verification (PQV) of advanced electronic packaging and interconnect technologies and various other types of qualification hardware for the Mars Exploration Rover/Mars Science Laboratory flight projects has been performed to enhance the mission assurance. The qualification of hardware (Engineering Camera and Platinum Resistance Thermometer, PRT) under extreme cold temperatures has been performed with reference to various project requirements. The flight-like packages, sensors, and subassemblies have been selected for the study to survive three times (3x) the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations and mission phases. Qualification has been performed by subjecting above flight-like qual hardware to the environmental temperature extremes and assessing any structural failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experiments of flight like hardware qualification test results have been described in this paper.

package reliability↗
NASA NTRS2007

Thermal Cycle Lifetest of Swaged Cathode Heaters

This viewgraph presentation reviews the thermal cycling test for the Dawn mission. The flight system, the mission requirements, and the Ion Propulsion System (IPS) are shown. The Dawn mission requires periodic thruster shutdown for data transmission and coast periods. The thermal cycling test is designed to simulate approximately three complete mission profiles. The results of the tests are reviewed.

ion engines↗
NASA NTRS2006

Functional Recovery of Analog Circuits at Extreme Temperatures

This paper describes a new reconfigurable analog array (RAA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.

self-recovery↗
NASA NTRS2006

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

self-recovery↗
NASA NTRS2006

Temperature-adaptive Circuits on Reconfigurable Analog Arrays

This paper describes a new reconfigurable analog array (MA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.

self recovery↗
NASA NTRS2005

Evolvable hardware system at extreme low temperatures

This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hardening-by-process and hardening-by-design, 'hardening-by-reconfiguration ', when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive selfreconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. This paper demonstrates this technique for circuit evolution and recovery at liquid nitrogen temperatures (-196.6 (deg)C). In addition, preliminary tests are performed to assess the survivability limitations of the evolutionary processor at extreme low temperatures.

evolvable harware↗
NASA NTRS2005

Re-Configurable Electronics Characterization under Extreme Thermal Environment

The need for reconfigurable electronics is driven by requirements to survive longer missions and harsher environments. It is possible to compensate for degradations in Extreme Environments (EE). EE has effect on electronics: circuits are designed to exploit device characteristics and when a certain temperature or radiation range is exceeded the circuit function gradually degrades. It is possible to employ Hardening by reconfiguration (HBR) to mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. In this manner degraded components can be salvaged, and completely damaged components can be bypassed. The challenge of conventional design is replaced with that of designing a recover process that automatically performs the (re) design in place of the designer. The objective of testing a Digital Signal Processor (DSP) under the extreme temperatures was to determine the lowest temperature at which the DAP can operate. The objective of testing a Xilinx VirtexII Pro FPGA board was to initially find our whether the evaluation board and the FPGA would survive and continue at temperature ranges from -180 C, and 120 C. The Virtex II functioned correctly at the temperatures tested. The next test was done on the GM-C filter building block using the same temperature range as the Virtex II. The current lower and upper limits were shown to be reduced as the temperature gets lower. The device function can be recovered by increasing the Vb from .08V to .85V. The negative and positive saturation voltages increases as the temperature gets higher. The function of the device can be recovered by decreasing the Vb from .8V to around .75V. The next test was performed to test the recovery of the GmC low pass filter through Vb in a filter circuit. The test indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures.

reliability↗
NASA NTRS2005

Preliminary low temperature tests of a digital signal processor

This paper describes an initial experiment performed to assess the electrical behavior of the Innovative Integration board containing a Digital Signal Processor (DSP) with its JTAG (Blackhawk) connector at low temperatures. The objective of the experiment is to determine the lowest temperature at which the DSP can operate. The DSP was tested at various low-temperatures and a Genetic Algorithm was used as the DSP test program.

temperatures↗
NASA NTRS2005

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

thermal cycling↗
NASA NTRS2004

Operation of FPGAs at Extremely Low Temperatures

This paper describes the operation of FPGAs at very low temperatures eg -160(deg)C. Both Actel and Xilinx parts are tested It was found that low temperature operations is not a problem with the parts tested, but there is a problem with powering on an FPGA at cold temperatures.

Field-Programmable Gate Array (FPGA)↗
NASA NTRS2003

Electronic nose for space program applications

The ability to monitor air contaminants in the shuttle and the International Space Station is important to ensure the health and safety of astronauts, and equipment integrity. Three specific space applications have been identified that would benefit from a chemical monitor: (a) organic contaminants in space cabin air; (b) hypergolic propellant contaminants in the shuttle airlock; (c) pre-combustion signature vapors from electrical fires. NASA at Kennedy Space Center (KSC) is assessing several commercial and developing electronic noses (E-noses) for these applications. A short series of tests identified those E-noses that exhibited sufficient sensitivity to the vapors of interest. Only two E-noses exhibited sufficient sensitivity for hypergolic fuels at the required levels, while several commercial E-noses showed sufficient sensitivity of common organic vapors. These E-noses were subjected to further tests to assess their ability to identify vapors. Development and testing of E-nose models using vendor supplied software packages correctly identified vapors with an accuracy of 70-90%. In-house software improvements increased the identification rates between 90 and 100%. Further software enhancements are under development. Details on the experimental setup, test protocols, and results on E-nose performance are presented in this paper along with special emphasis on specific software enhancements. c2003 Elsevier Science B.V. All rights reserved.

Air Pollution, Indoor/analysis↗