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Spry, David J.

Publications and source records attributed to Spry, David J..

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Microelectronics↗
NASA NTRS2015

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

High temperature↗
NASA NTRS2014

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Microelectronics↗
NASA NTRS2014

Structural Characterization of Lateral-grown 6H-SiC am-plane Seed Crystals by Hot Wall CVD Epitaxy

The performance of commercially available silicon carbide (SiC) power devices is limited due to inherently high density of screw dislocations (SD), which are necessary for maintaining polytype during boule growth and commercially viable growth rates. The NASA Glenn Research Center (GRC) has recently proposed a new bulk growth process based on axial fiber growth (parallel to the c-axis) followed by lateral expansion (perpendicular to the c-axis) for producing multi-faceted m-plane SiC boules that can potentially produce wafers with as few as one SD per wafer. In order to implement this novel growth technique, the lateral homoepitaxial growth expansion of a SiC fiber without introducing a significant number of additional defects is critical. Lateral expansion is being investigated by hot wall chemical vapor deposition (HWCVD) growth of 6H-SiC am-plane seed crystals (0.8mm x 0.5mm x 15mm) designed to replicate axially grown SiC single crystal fibers. The post-growth crystals exhibit hexagonal morphology with approximately 1500 m (1.5 mm) of total lateral expansion. Preliminary analysis by synchrotron white beam x-ray topography (SWBXT) confirms that the growth was homoepitaxial, matching the polytype of the respective underlying region of the seed crystal. Axial and transverse sections from the as grown crystal samples were characterized in detail by a combination of SWBXT, transmission electron microscopy (TEM) and Raman spectroscopy to map defect types and distribution. X-ray diffraction analysis indicates the seed crystal contained stacking disorders and this appears to have been reproduced in the lateral growth sections. Analysis of the relative intensity for folded transverse acoustic (FTA) and optical (FTO) modes on the Raman spectra indicate the existence of stacking faults. Further, the density of stacking faults is higher in the seed than in the grown crystal. Bundles of dislocations are observed propagating from the seed in m-axis lateral directions. Contrast extinction analysis of these dislocation lines reveals they are edge type basal plane dislocations that track the growth direction. Polytype phase transition and stacking faults were observed by high-resolution TEM (HRTEM), in agreement with SWBXT and Raman scattering.

Single Crystal↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗
NASA NTRS2011

High Temperature Capacitive Pressure Sensor Employing a SiC Based Ring Oscillator

In an effort to develop harsh environment electronic and sensor technologies for aircraft engine safety and monitoring, we have used capacitive-based pressure sensors to shift the frequency of a SiC-electronics-based oscillator to produce a pressure-indicating signal that can be readily transmitted, e.g. wirelessly, to a receiver located in a more benign environment. Our efforts target 500 C, a temperature well above normal operating conditions of commercial circuits but within areas of interest in aerospace engines, deep mining applications and for future missions to the Venus atmosphere. This paper reports for the first time a ring oscillator circuit integrated with a capacitive pressure sensor, both operating at 500 C. This demonstration represents a significant step towards a wireless pressure sensor that can operate at 500 C and confirms the viability of 500 C electronic sensor systems.

Meredith, Roger D.↗
NASA NTRS2011

Lateral Growth Expansion of 4H/6H-SiC m-plane Pseudo Fiber Crystals by Hot Wall CVD Epitaxy

Lateral expansion of small mixed polytype 4H/6H-SiC slivers were realized by hot wall chemical vapor deposition (HWCVD). Small slivers cut from m-oriented ..11..00.. SiC boule slices containing regions of 4H and 6H SiC were exposed to HWCVD conditions using standard silane/propane chemistry for a period of up to eight hours. The slivers exhibited approximately 1500 microns (1.5 mm) of total lateral expansion. Initial analysis by synchrotron white beam x-ray topography (SWBXT) confirms, that the lateral growth was homoepitaxial, matching the polytype of the respective underlying region of the seed sliver.

Trunek, Andrew J.↗
NASA NTRS2011

SiC growth by Solvent-Laser Heated Floating Zone

In an effort to grow single crystal SiC fibers for seed crystals the following two growth methods have been coupled in this work: traveling solvent and laser heated floating zone to create the solvent-laser heated floating zone (Solvent-LHFZ) crystal growth method. This paper discusses the results of these initial experiments, which includes: source material, laser heating, and analysis of the first ever Solvent-LHFZ SiC crystals (synchrotron white beam x-ray topography confirmed).

Woodworth, Andrew A.↗
NASA NTRS2008

Method for the growth of large low-defect single crystals

A method and the benefits resulting from the product thereof are disclosed for the growth of large, low-defect single-crystals of tetrahedrally-bonded crystal materials. The process utilizes a uniquely designed crystal shape whereby the direction of rapid growth is parallel to a preferred crystal direction. By establishing several regions of growth, a large single crystal that is largely defect-free can be grown at high growth rates. This process is particularly suitable for producing products for wide-bandgap semiconductors, such as SiC, GaN, AlN, and diamond. Large low-defect single crystals of these semiconductors enable greatly enhanced performance and reliability for applications involving high power, high voltage, and/or high temperature operating conditions.

Powell, J. Anthony↗
NASA NTRS2008

Prolonged 500 C Operation of 6H-SiC JFET Integrated Circuitry

This paper updates the long-term 500 C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 degC with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 C before failure.

Neudeck, Philip G.↗
NASA NTRS2008

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

Neudeck, Philip G.↗
NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗