NASA NTRS · 19830006722
The VLSI design of a single chip Reed-Solomon encoder
Abstract
A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.
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Truong, T. K., Deutsch, L. J., Reed, I. S.. 1982-11-15. The VLSI design of a single chip Reed-Solomon encoder. https://ntrs.nasa.gov/citations/19830006722
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