Dislocation half-loop control for optimal V-defect density in GaN-based light emitting diodes

Abstract

V-defects are morphological defects that typically form on threading dislocations during epitaxial growth of $(0001)$-oriented GaN layers. A V-defect is a hexagonal pyramid-shaped depression with six {$10\bar{1}1$}-oriented sidewalls. These semipolar sidewalls have a lower polarization barrier than the polarization barriers present between the polar c-plane quantum wells and quantum barriers and can laterally inject carriers directly into quantum wells in GaN-based light emitting diodes (LEDs). This is especially important, as the high polarization field in c-plane GaN is a significant factor in the high forward voltage of GaN LEDs. The optimal V-defect density for efficient lateral carrier injection in a GaN LED (∼10 9 cm −2 ) is typically an order of magnitude higher than the threading dislocation density of GaN grown on patterned sapphire substrates (∼10 8 cm −2 ). Pure-edge dislocation loops have been known to exist in GaN, and their formation into large V-defects via low-temperature growth with high Si-doping has recently been studied. Here, in this work, we develop a method for pure-edge threading dislocation half-loop formation and density control via disilane flow, growth temperature, and thickness of the half-loop generation layer. We also develop a method of forming the threading dislocation half-loops into V-defects of comparable size to those originating from substrate threading dislocations.