Application of scanning electron microscopy to integrated circuit failure
Integrated circuit failure analysis with scanning electron microscopy taking into account ball bond contamination and open metallization at contact windows
Devaney, J. R.↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Application of acoustic surface wave technology to shuttle radar
The application of surface acoustic wave (SAW) signal processing devices in the space shuttle was explored. In order to demonstrate the functions which a SAW device might perform, a breadboard pulse compression filter (PCF) module was assembled. The PCF permits a pulse radar to operate with a large duty cycle and low peak power, a regime favorable to the use of solid state RF sources. The transducer design, strong coupling compensation, circuit model analysis, fabrication limitations, and performance evaluation of a PCF are described. The nominal value of the compression ratio is 100:1 with 10-MHz bandwidth centered at 60 MHz and 10-microsecond dispersive delay. The PCF incorporates dispersive interdigital transducers and a piezoelectric lithium niobate substrate.
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Formal semantics for a subset of VHDL and its use in analysis of the FTPP scoreboard circuit
In the first part of the report, we give a detailed description of an operational semantics for a large subset of VHDL, the VHSIC Hardware Description Language. The semantics is written in the functional language Caliban, similar to Haskell, used by the theorem prover Clio. We also describe a translator from VHDL into Caliban semantics and give some examples of its use. In the second part of the report, we describe our experience in using the VHDL semantics to try to verify a large VHDL design. We were not able to complete the verification due to certain complexities of VHDL which we discuss. We propose a VHDL verification method that addresses the problems we encountered but which builds on the operational semantics described in the first part of the report.
Bickford, Mark↗
Life Cycle Analysis of a SpaceCube Printed Circuit Board Assembly Using Physics of Failure Methodologies
In this reliability life cycle evaluation of the SpaceCube 2.0 processor card, a partially populated version of the card is being evaluated to determine its durability with respect to typical GSFC mission loads.
Virtual Qualification↗
Design and Analysis of Broad-Band Fixed-Tuned Submillimeter-Waveguide Multipliers using MMIC Style Circuit Topology
The design and analysis of varactor diode doubler, quadrupler and cascaded doubler circuits for 320 and 640 GHz have been completed. A new approach has been employed to produce a tunerless waveguide mount with a very flexible, frequency scaleable, MMIC style multiplier circuit. The concept, design, predicted performance and measurements on some of the constituent mount elements are presented.
varactor diode doubler MMIC style multiplier circu↗
Management of reliability and maintainability; a disciplined approach to fleet readiness
Material acquisition fundamentals were reviewed and include: mission profile definition, stress analysis, derating criteria, circuit reliability, failure modes, and worst case analysis. Military system reliability was examined with emphasis on the sparing of equipment. The Navy's organizational strategy for 1980 is presented.
Willoughby, W. J., Jr.↗
A Twin Circuit Theory-Based Framework for Oscillation Event Analysis in Inverter-Dominated Power Systems With Case Study for Kaua‘i System
Here, this paper proposes a real-world oscillation event analysis framework for power systems that include inverter-based resources together with synchronous generators. Specifically, the proposed framework combines both measurement-and model-based techniques to readily identify potential oscillation sources, replay the oscillation event with numerical simulation, unveil the underlying oscillation mechanism, and suggest mitigation methods for a wide range of oscillation events. To strengthen the theoretical foundation of our analysis framework, this paper proposes a twin circuit theory that provides theoretical support for one key utilized but not well-proven measurement-based oscillation source identification method-Dissipating Energy Flow. Our twin circuit theory also shows that adopting well-tuned grid-forming inverters can be a potential mitigation method for oscillation events. Finally, the effectiveness of our proposed oscillation event analysis framework is demonstrated by addressing a real-world 18-20 Hz oscillation event in Kaua‘i's power system on November 21, 2021.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Computer-assisted circuit engineering
Accurate circuit parameter characterization, flexible network analysis computer programs, and empirical circuit responses for designing of circuits
COMPUTER PROGRAM↗
Harmonic analysis approach to the 'TunneLadder' - A modified Karp circuit for millimeter-wave TWTA's
A field approach to the summed harmonic analysis of the TunneLadder structure, or modified forward-wave Karp circuit, is developed by combining TM(01) and TE(11) modes. Results suggest the suitability of this structure as a high-impedance, about 1-% bandwidth circuit, millimeter-wave forward-wave-type amplifier that is voltage tunable over about a 5-% frequency range and has excellent power handling ability. Theory gives good agreement with experimental results obtained by Karp in omega-beta dispersion and predicts qualitatively the appearances of the antisymmetric mode discussed and of the so called Hightron mode that was discussed earlier in White, Enderby and Birdsall (1964), and Enderby (1964), in addition to the desired symmetric mode.
Kosmahl, H. G.↗
Carrier synchronization techniques for unbalanced QPSK signals. I
This paper uses MAP estimation techniques to obtain carrier reconstruction circuits for unbalanced QPSK signals. In addition, the performance analysis of these circuits is carried out to the extent that a loop design can proceed. Numerical results are presented in order to demonstrate the utility of the theory developed. This signal design will be used in the development of the Tracking and Data Relay Satellite System (TDRSS) and the Navigation Satellite Timing and Ranging Global Positioning System (NAVSTAR GPS).
Braun, W. R.↗
The effect of a defective BSF layer on solar cell open circuit voltage
A straightforward analysis of special limiting cases has permitted the determination of the range of possible open circuit voltage losses due to a defective BSF (back surface field) layer. An important result of the analysis is the finding that it is possible to have a fully effective BSF region, regardless of the spatial distribution of the defective areas, as long as the total defective area is reduced below certain limits. Distributed defects were found to be much more harmful than lumped defects.
Weizer, V. G.↗
Data Transfer Efficiency Over Satellite Circuits Using a Multi-Socket Extension to the File Transfer Protocol (FTP)
In several experiments using NASA's Advanced Communications Technology Satellite (ACTS), investigators have reported disappointing throughput using the transmission control protocol/Internet protocol (TCP/IP) protocol suite over 1.536Mbit/sec (T1) satellite circuits. A detailed analysis of file transfer protocol (FTP) file transfers reveals that both the TCP window size and the TCP 'slow starter' algorithm contribute to the observed limits in throughput. In this paper we summarize the experimental and and theoretical analysis of the throughput limit imposed by TCP on the satellite circuit. We then discuss in detail the implementation of a multi-socket FTP, XFTP client and server. XFTP has been tested using the ACTS system. Finally, we discuss a preliminary set of tests on a link with non-zero bit error rates. XFTP shows promising performance under these conditions, suggesting the possibility that a multi-socket application may be less effected by bit errors than a single, large-window TCP connection.
Allman, Mark↗
Bridging the Gap on Data and Analysis for Distribution System Planning: Information That Utilities Can Provide Regulators, State Energy Offices and Other Stakeholders
Electric utilities conduct planning annually to ensure their distribution system meets technical standards, policies, and regulations; addresses forecasted grid conditions; satisfies customer needs; and advances utility priorities. The plan identifies grid deficiencies, analyzes potential solutions, and prioritizes capital investments and other expenditures. About 20 U.S. states and jurisdictions require regulated utilities to file some type of distribution system plan with the public utility commission for review. Requirements for sharing distribution system data and analyses vary widely, from few specific requirements to a detailed list of information that must be provided. While utilities conduct extensive analysis to develop distribution system plans, in most jurisdictions regulators and stakeholders do not know what data are available and how the utility uses the data in planning and investing. This report aims to bridge the gap by increasing understanding of the types of data and analyses utilities employ to develop distribution system plans and how the information affects their decision-making. The report describes information that states and stakeholders can ask for related to 11 data categories: -Forecasting loads and distributed energy resources (DERs) -Scenario analysis -Worst-performing circuits -Asset management strategy -Hosting capacity analysis -Value of DERs -Grid needs assessment -Cost-effectiveness framework for investments -Distribution system investment strategy and implementation -Geotargeted programs -Non-wires alternatives procurements.
24 POWER TRANSMISSION AND DISTRIBUTION↗
A current-excited large-signal analysis of IMPATT devices and its circuit implications.
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Gupta, M.-S.↗
Yield analysis of large capacity magnetic bubble circuits with redundancy design
The fabrication yield of an on-chip modifiable redundant circuit design for a 100M bit serial shift register is evaluated. The yield model is a redundancy design in which there is a primary loop and a set of secondary loops which can be enabled/disabled without introducing blanks to the data stream. This function has a finite yield, the loop-modification yield factor, which must be greater than 0.9 to make the system more economical than the simple nonredundant design. It is further established that small loop capacities greatly degrade the yield because of the effect of the modification yield factor, while large loop capacities degrade the yield because of defects in the operating area. As the modification yield increases the optimum loop capacity decreases. An optimum value for the number of redundant loops exists for each loop capacity. Other factors that affect the yield are the garnet film and the processed circuit.
Bailey, R. F.↗
Analysis of bilinear noise models in circuits and devices
There are a number of applications in which linear noise models are inappropriate. In the paper, the use of bilinear noise models in circuits and devices is considered. Several physical problems are studied in this framework. These include circuits involving varying parameters (such as variable resistance circuits constructed using field-effect transistors), the effect of switching jitter on sampled data system performance and communication systems involving voltage-controlled oscillators and phase-lock loops. In addition, several types of analytical techniques for stochastic bilinear systems are considered. Specifically, the moment equations of Brockett for bilinear systems driven by white noise are discussed, and closed-form expressions for certain bilinear systems (those that evolve an Abelian or solvable Lie groups) driven by white or colored noise are derived. In addition, an approximate statistical technique involving the use of harmonic expansions is described.
Willsky, A. S.↗
Fault detection in digital and analog circuits using an i(DD) temporal analysis technique
An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.
Beasley, J.↗
Development of a plan for automating integrated circuit processing
The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.
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