MOS field-effect transistor drivers for laminated-ferrite memories.
MOSFET drivers for low current memory fabricated in 64 unit monolithic strips, discussing driver performance data
Boesenberg, W. A.↗
SEARCH · Search NASA
Results for “mos”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Combined MOS and radiochemical analysis of impurities in SiO sub 2 on Si.
Oxide impurity effects causing potential shifts in Si covered by thick oxide layer studied with metal-oxide-Si electrical measurement and radiochemical analysis
Kuper, A. B.↗
Deposition of MoS sub 2 films by physical sputtering and their lubrication properties in vacuum.
Physical sputtering deposition of molybdenum disulfide films as solid lubricant on rotating and sliding components, discussing lubrication properties in vacuum
Spalvins, T.↗
How reliable are MOS ICs - As good as bipolars, says NASA.
Metal oxide semiconductor integrated circuits, showing failure rates and degradation causes
Hamiter, L. C., Jr.↗
Technique for producing bipolar and MOS field effect transistors on a single chip
Several cycles of photoetching, dopant deposition, and drive-in produce selectively-doped regions and semiconductor junctions within a single chip.
Gallagher, R. C.↗
Complementary-MOS binary counter with parallel-set inputs
Metal oxide semiconductor four-stage binary counter contains reset capability as well as four parallel-set inputs gated in by a logic signal. Parallel-set inputs permit setting the counter into any of sixteen possible states.
Keller, K. R.↗
Complementary MOS and bipolar make it together on a single chip
Complementary metal oxide semiconductor and bipolar transistors fabrication on same integrated circuit chip by C-squared technology
Cook, R.↗
Radiation effects in MOS integrated circuits
High energy electron irradiation effects on field effect transistors in integrated circuit devices
Brashears, S. S.↗
Forecasting of the performance of MOS device for space applications
Analysis of radiation damage of MOSFET data from Explorer 34 (IMP-F), and radiation damage characteristics of MOSFET with boron diffused between a silicon semiconductor and silicon oxide are considered. The first subject is an interpretation of the discrepancy between the space data and the laboratory data. The second subject is an attempt to analyze the radiation damage characteristic of MOSFET when there is modification of electrical properties in the gate oxide region.
Fang, P. H.↗
Complementary MOS four-phase logic circuits
Technique can provide four-phase clock signal from single-phase clock and requires only one power supply voltage. This arrangement saves considerable power compared to circuits having load resistor between power supply and ground.
Petersen, H. L.↗
C-MOS array design techniques: SUMC multiprocessor system study
The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.
Clapp, W. A.↗
Performance of hardened P-MOS devices in severe neutron environments.
Explore the source record for details and available documents.
Aubuchon, K. G.↗
Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron
Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.
Danchenko, V.↗
A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistor
Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
Halsor, J. L.↗
Integrated P-channel MOS gyrator
A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.
Hochmair, E. S.↗
Tunneling through thin MOS structures - Dependence on energy /E-kappa/
The tunneling characteristics of Cr/SiO2/Si structures in the thickness range from 23 to 34 A are reported. The E-kappa dependence in the energy range extending 3.5 eV below the oxide conduction band is determined by the thickness dependence to be approximately of the Franz form with an effective mass ratio of 0.42. Tunneling into the indirect conduction band of silicon is reduced by a thickness-independent factor which decreases approximately exponentially with the energy below the direct band edge.
Maserjian, J.↗
Resonance effects observed at the onset of Fowler-Nordheim tunneling in thin MOS structures
Explore the source record for details and available documents.
Petersson, G. P.↗
An optimized output stage for MOS integrated circuits
An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
Lin, H. C.↗