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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Fabrication method is described for alumina passivated silicon MISFET arrays. Technique involves total passivation beam-lead approach and provides completely sealed chip with double level interconnect capability. Refractory metal alloy is used to form interconnect system and obtain metal contacts that withstand temperatures of 873 K for short periods of time.
Rotating magnetic field of bubble domain memory is used to obtain time-division multiplexing of bubble domain circuits into quadrants. Memory bits are assigned on bit-per-chip rather than bit-per-module basis; power is reduced by circulating only portion of bubbles at a time.
In the assembly of hybrid microcircuits, passive and active discrete chip components are attached by epoxy cements and by solders. This study was initiated to determine the integrity of such attachments. Alumina substrates were subjected to a group of thermal and mechanical test environments defined by test methods in MIL-STD-883. Lot samples of substrates with assembly variations were subjected to separately applied testing and to serial testing. These test methods were applied sequentially to the same lot of substrates. Epoxy cements were generally satisfactory with respect to separate tests, although sequential tests severely degraded epoxy bond strengths of all types. Bond strengths to unglazed substrates were slightly superior to those of the same components on glazed types. Solder joints were vulnerable to catastrophic failure in several environments, especially temperature cycling and thermal shock. Vibration and impact shock also produced solder joint failures.
The thermal expansion coefficients of a representative sample of BaTiO3 and TiO2 ceramic chip capacitors and alumina substrates have been examined. These data have revealed large potential mechanical stresses under thermal cycling. A mathematical analysis of a composite model of the capacitor to predict the thermal expansion and modulus of elasticity and an analysis of the capacitor-substrate system to predict the magnitude of thermally induced stresses have been conducted. In all cases studied, thermally induced stresses great enough to cause capacitor body rupture or termination failure was predicted.
A noncryogenic, S-band parametric amplifier operating in the 2.2 to 2.3 GHz band and having an average input noise temperature of less than 30 K was built and tested. The parametric amplifier module occupies a volume of less than 1-1/4 cubic feet and weighs less than 60 pounds. The module is designed for use in various NASA ground stations to replace larger, more complex cryogenic units which require considerably more maintenance because of the cryogenic refrigeration system employed. The amplifier can be located up to 15 feet from the power supply unit. Optimum performance was achieved through the use of high-quality unpackaged (chip) varactors in the amplifier design.
Special chuck directs mixture of pressurized air and water through drill bit, thus removing chips during boring of long, large diameter holes.
Proposed field-effect transistor consists of three cells which make up one complete FET pellet. Pellet is flip-chip mounted on carrier with source grounded gate and drain posts connected directly to impedance-matching transmission-line segments. Impedance transformers are part of mounting and contact strips.
Reamer shaft is modified by central passage and intake and outlet slots. To help draw away chips and lubricant and augment vacuum, positive pressure is applied inside orifice of part being reamed. Tool especially useful when surroundings must be kept free from contamination.
Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault tolerant computer was modeled. An efficient approach to functional fault simulation was developed. Simulation software was also developed.
Chip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed.
Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.
It is pointed out that the NASA 30/20 GHz program will place in geosynchronous orbit a technically advanced communication satellite which can process time-division multiple access (TDMA) information bursts with a data throughput in excess of 4 GBPS. To guarantee acceptable data quality during periods of signal attenuation it will be necessary to provide a significant forward error correction (FEC) capability. Convolutional decoding (utilizing the maximum-likelihood techniques) was identified as the most attractive FEC strategy. Design trade-offs regarding a maximum-likelihood convolutional decoder (MCD) in a single-chip CMOS implementation are discussed.
A CCD technique is described which allows long integration periods between readouts together with moderate chopping rates. During each phase of a differential chopping cycle, one set of charge images is shifted to the center of the chip, which is light sensitive. At the same time, the other set of charge images is shifted under one of two masked areas which serve as charge-storage sites. Since the vertical shifting between phases can be accomplished in much less time than the typical exposure per phase, there is negligible image smearing. For a given light level and chopping rate the performance of this technique is limited primarily by the readout noise and the vertical charge transfer inefficiency. If many transfer cycles are required between readouts, the charge transfer inefficiency will diffuse the accumulated charge images along the vertical columns. Laboratory and astronomical data obtained with this technique using a CCD camera and the 2.3 m telescope on Kitt Peak are presented.
Low noise and linearity of charge-coupled devices (CCD's) combined with optical waveguide components in hybrid, integrated chip package. Concept used to measure laser flux in fiber-gyro application using sensing fibers that range from several to several tens of kilometers in length. Potential applications include optical delay measurement and linear detector of light flux emanating from fiber-optic waveguides.
A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.
A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.
Universal method of bonding laser-diode chip to mount developed. New technique applicable to almost all different types of mounts used in production of laser diodes. Submounts etched, then cut from metal foil. Advantage of this type of submount is edge on which diode mounted is very sharp, eliminating costly need for sharp edge on mount itself.