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Results for “Digital Fabrication”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Thermographic phosphor digital image correlation

The invention advances the ratio method of phosphor thermography using two machine vision cameras for full-field temperature measurements of a solid surface. As an example, algorithms from digital image correlation (DIC) can be used to determine the stereoscopic imaging system intrinsic and extrinsic parameters, and accurately register material points on the sample to subpixel locations in each image with 0.07 px or better accuracy. A phosphor calibration sample fabricated using aerosol deposition can be used for in situ determination of the temperature-versus-intensity ratio relationship. The full calibration methodology and several improvements on two-color phosphor thermography open the door for full-field temperature measurements in dynamic tests with deforming test specimens. In particular, thermographic phosphors can be combined with stereo digital image correlation in a novel diagnostic, TP+DIC, to measure time-resolved full-field surface strains and temperatures simultaneously, thereby enabling testing in combined thermo-mechanical environments.

Winters, Caroline↗
DOE OSTI2024

The 650 °C Tensile Deformation of Graded IN718-René41 Superalloy Fabricated by Laser Blown-Powder Directed Energy Deposition

The microstructure and 650 °C tensile properties of a compositionally graded IN718-René41 (718-R41) superalloy fabricated by laser blown-powder directed energy deposition (DED-LB/M) are investigated to understand structure–property relationships and baseline tensile properties. Digital Image Correlation (DIC), in situ neutron diffraction, and conventional characterization techniques are performed to study the as-built and heat-treated states. The applied heat treatment generates static recrystallization and equiaxed grains in 718-rich compositions, while R41-rich compositions remain partially or un-recrystallized possibly influenced by a higher MC carbide fraction (>0.5%). The yield strengths of the 718 and R41 sections in the heat-treated state are comparable to wrought forms but the graded compositions show weakness due to unoptimized heat treatment. Diffraction elastic constants first decrease and then increase along the 718-R41 composition gradient, while a small difference is observed between the as-built and heat-treated states and γ, γ′ phases. Overall, the compositionally graded region shows a smooth transition in the elastic properties. Grain-level load transfer from the (220) to (200) grains shows compositional dependence, and qualitatively agrees with DIC-measured macroscopic yield strength. Within the (200) grains, the γ/γ′ phases deform elastically until the γ phase yields and afterwards, the γ′ phase takes load from the γ phase.

Huang, Shenyan (ORCID:0000000196528114)↗
NASA NTRS1989

Gallium arsenide processing for gate array logic

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Cole, Eric D.↗
NASA NTRS1998

Design and Specification of Optical Bandpass Filters for Hubble Space Telescope (HST) Advanced Camera for Surveys (ACS)

Advanced optical bandpass filters for the Hubble Space Telescope (HST) Advanced Camera for Surveys (ACS) have been developed on a filter-by-filter basis through detailed studies which take into account the instrument's science goals, available optical filter fabrication technology, and developments in ACS's charge-coupled-device (CCD) detector technology. These filters include a subset of filters for the Sloan Digital Sky Survey (SDSS) which are optimized for astronomical photometry using today's charge-coupled-devices (CCD's). In order for ACS to be truly advanced, these filters must push the state-of-the-art in performance in a number of key areas at the same time. Important requirements for these filters include outstanding transmitted wavefront, high transmittance, uniform transmittance across each filter, spectrally structure-free bandpasses, exceptionally high out of band rejection, a high degree of parfocality, and immunity to environmental degradation. These constitute a very stringent set of requirements indeed, especially for filters which are up to 90 mm in diameter. The highly successful paradigm in which final specifications for flight filters were derived through interaction amongst the ACS Science Team, the instrument designer, the lead optical engineer, and the filter designer and vendor is described. Examples of iterative design trade studies carried out in the context of science needs and budgetary and schedule constraints are presented. An overview of the final design specifications for the ACS bandpass and ramp filters is also presented.

Leviton, Douglas B.↗
DOE OSTI2023

Microscale drivers and mechanisms of fracture in post-processed additively manufactured Ti–6Al– 4 V

Herein, we focus on understanding the microstructure-fracture correlations in a Ti–6Al– 4 V alloy additively manufactured via electron beam melting (EBM) and subjected to various post-process heat-treatments. Specifically, the as fabricated material is subjected to a sub-transus heat-treatment followed by air-cooling and a super-transus heat-treatment followed by either air- or furnace-cooling. Next, a series of in-situ single edge notch tension (SENT) tests are carried out under a high-resolution digital optical microscope. The panoramic high-resolution images captured during the in-situ tests are then used to characterize the planar deformation on the specimen surface using microstructure-based digital image correlation (DIC). Additionally, the results of the in-situ SENT tests together with DIC and post-mortem fractographic analyses provided us with a better understanding of the microstructure-fracture correlations in these materials. Our results show that the fracture mechanism of the as fabricated and sub-transus heat-treated materials is essentially the same, while the changes in the microstructure following the super-transus heat-treatments significantly affects the fracture mechanism. In this case, several microcracks of hundreds of microns in length first nucleate away from the deformed notch following extreme plastic deformation at discrete locations. Furthermore, the location of these microcracks in the super-transus heat-treated materials is extremely sensitive to the details of the underlying microstructure.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗
NASA NTRS1995

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗
DOE OSTI2020

Assessment of the Material Performance for TCR Applications (Progress Report)

The objective of Argonne’s materials research activities for the Transformational Challenge Reactor (TCR) program is to improve the understanding of material properties from additive manufacturing with the focus on understanding the creep and fatigue properties of additively manufactured materials. The material work conducted by Argonne provides support in developing and qualifying advanced materials and manufacturing processes to allow for innovative reactor design and licensing for the TCR. In FY 2020, Oak Ridge National Laboratory (ORNL) provided six ASTM standard sized creep specimens of additively-manufactured 316L stainless steel (AM 316L SS) for evaluation of the effect of post-build heat treatment on the creep property. Two different teat treatments were conducted on the as-built specimens, namely 1050°C/1h and 650°C/1h before creep testing. All specimens were creep tested at 550°C and 275 MPa to understand the effect of heat treatments. We have also received AM 316L SS printed in various forms including rods and sheets, wrought 316 L SS (as a reference material), and AM IN718 for tensile, creep and fatigue testing. Both ASTM standard sized specimens and subsized specimens are being fabricated or tested to contribute to a comprehensive mechanical property database of AM materials and to provide location-specific property data to the TCR digital platform. Mechanical testing at Argonne is conducted to ASME NQA-1 or its lab equivalent for quality assurance. This report presents the results of the creep tests at 550°C and microstructural characterization for the assessment of the effect of the post-build heat treatment on the creep behavior of AM 316L SS. It also discusses ongoing efforts on obtaining location-dependent properties of AM 316L SS.

36 MATERIALS SCIENCE↗
NASA NTRS1973

Digital capacitance measuring system

The hardware phase of a digital capacitance measuring system is presented with the major emphasis placed on the electrical design and operation. Test results are included of the three units fabricated. The system's interface is applicable to existing requirements for the space shuttle vehicle.

Source record↗
NASA NTRS1974

A membrane page composer - Further developments

Membrane page composers were made and were evaluated in a simulated holographic optical memory system. Calculated and experimentally determined electromechanical and optical characteristics of the circular membrane light valves used on the arrays are shown to be in close agreement. Several operating prototypes of 8 x 8 and 16 x 16 elements were produced. Measurements were made of switching time, optical contrast, and dynamic storage time of many cells on the devices. Digital patterns were stored in the arrays. The performance required of the page composer as a component of an optical memory system is considered. The fabrication techniques used can be easily extended to larger arrays.

Cosentino, L. S.↗
NASA NTRS1976

Quiet Clean Short-haul Experimental Engine (QCSEE) preliminary under the wing flight propulsion system analysis report

The preliminary design and installation of high bypass, geared turbofan engine with a composite nacelle forming the propulsion system for a short haul passenger aircraft are described. The technology required for externally blown flap aircraft with under the wing (UTW) propulsion system installations for introduction into passenger service in the mid 1980's is included. The design, fabrication, and testing of this UTW experimental engine containing the required technology items for low noise, fuel economy, with composite structure for reduced weight and digital engine control are provided.

Howard, D. F.↗
DOE OSTI2023

Customized Nanostructured Ceramics via Microphase Separation 3D Printing

To date, the restricted capability to fabricate ceramics with independently tailored nano- and macroscopic features has hindered their implementation in a wide range of crucial technological areas, including aeronautics, defense, and microelectronics. In this study, a novel approach that combines self- and digital assembly to create polymer-derived ceramics with highly controlled structures spanning from the nano- to macroscale is introduced. Polymerization-induced microphase separation of a resin during digital light processing generates materials with nanoscale morphologies, with the distinct phases consisting of either a preceramic precursor or a sacrificial polymer. By precisely controlling the molecular weight of the sacrificial polymer, the domain size of the resulting material phases can be finely tuned. Pyrolysis of the printed objects yields ceramics with complex macroscale geometries and nanoscale porosity, which display excellent thermal and oxidation resistance, and morphology-dependent thermal conduction properties. This method offers a valuable technological platform for the simplified fabrication of nanostructured ceramics with complex shapes.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2021

Quantum Computer-Aided Design: Digital Quantum Simulation of Quantum Processors

With the increasing size of quantum processors, submodules that constitute the processor hardware will become too large to accurately simulate on a classical computer. Therefore, one would soon have to fabricate and test each new design primitive and parameter choice in time-consuming coordination between design, fabrication, and experimental validation. Here we show how one can design and test the performance of next-generation quantum hardware—by using existing quantum computers. Focusing on superconducting transmon processors as a prominent hardware platform, we compute the static and dynamic properties of individual and coupled transmons. We show how the energy spectra of transmons can be obtained by variational hybrid quantum-classical algorithms that are well suited for near-term noisy quantum computers. In addition, single- and two-qubit gate simulations are demonstrated via Suzuki-Trotter decomposition. Our methods pave a promising way towards designing candidate quantum processors when the demands of calculating submodule properties exceed the capabilities of classical computing resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRS1976

A precision star tracker utilizing advanced techniques and materials

An image dissector star tracker has been developed which operates in the photon counting mode making it possible to utilize all digital electronics. A unique pulse processing circuit allows bright stars to be tracked as well as dim stars. Thermal mechanical stability has been greatly enhanced by fabricating a housing with graphite/epoxy composite material with a linear coefficient of thermal expansion near zero. Test results indicate the +10 Mv stars can be acquired and tracked, while position variation with star intensity is less than 2 arc seconds from 2.5 Mv to +10 Mv. The noise equivalent angle for a +8 Mv star is 3 arc seconds. Polynominal correction for remaining cross-coupling and nonlinearity reduced error over total 1 x 1 deg field to 1.5 arc seconds.

Gates, R. F.↗
NASA NTRS1981

Forming electrical interconnections through semiconductor wafers

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗