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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

X-Ray-Diffraction Tests Of Irradiated Electronic Devices: I

X-ray-diffraction tests performed on aluminum conductors in commercial HI1-507A complementary metal oxide/semiconductor (CMOS) integrated-circuit analog multiplexers, both before and after circuits exposed to ionizing radiation from Co(60) source, and after postirradiation annealing at ambient and elevated temperatures. Tests in addition to electrical tests performed to determine effects of irradiation and of postirradiation annealing on electrical operating characteristics of circuits. Investigators sought to determine whether relationship between effects of irradiation on devices and physical stresses within devices. X-ray diffraction potentially useful for nondestructive measurement of stresses.

Shaw, David C.↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
NASA NTRS1990

Using advanced microelectronic test chips to qualify ASIC's for space

Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

Buehler, M. G.↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1979

Multiple-sample holder for IC testing

Carrousel tray speeds up testing process by feeding mass spectrometer up to 12 sealed integrated circuit packages in rapid succession for analysis of contaminants and total gas composition.

Haack, R. F.↗
NASA NTRS1989

Ka-band MMIC beam steered transmitter array

A 32-GHz six-element linear transmitter array utilizing monolithic microwave integrated circuit (MMIC) phase shifters and power amplifiers was designed and tested as part of the development of a spacecraft array feed for NASA deep-space communications applications. Measurements of the performance of individual phase shifters, power amplifiers, and microstrip radiators were carried out, and electronic beam steering of the linear array was demonstrated. The switched-line phase shifters were accurate to within 7 percent on average and the power amplifier 1-dB compressed output power varied over 0.3 dB. The array had a beamwidth of 7.5 deg and demonstrated acceptable beam steering over + or - 8 deg. From the results, it can be concluded that this MMIC phased array has adequate beam-scanning capability for use in the two-dimensional array. The areas that need to be improved are the efficiency of the MMIC power amplifier and the insertion loss of the MMIC phase shifter.

Rascoe, D. L.↗
NASA NTRS1991

Power electronics for low power arcjets

In anticipation of the needs of future light-weight, low-power spacecraft, arcjet power electronics in the 100 to 400 W operating range were developed. Limited spacecraft power and thermal control capacity of these small spacecraft emphasized the need for high efficiency. Power topologies similar to those in the higher 2 kW and 5 to 30 kW power range were implemented, including a four transistor bridge switching circuit, current mode pulse-width modulated control, and an output current averaging inductor with an integral pulse generation winding. Reduction of switching transients was accomplished using a low inductance power distribution network, and no passive snubber circuits were necessary for power switch protection. Phase shift control of the power bridge was accomplished using an improved pulse width modulation to phase shift converter circuit. These features, along with conservative magnetics designs allowed power conversion efficiencies of greater than 92.5 percent to be achieved into resistive loads over the entire operating range of the converter. Electromagnetic compatibility requirements were not considered in this work, and control power for the converter was derived from AC mains. Addition of input filters and control power converters would result in an efficiency of on the order of 90 percent for a flight unit. Due to the developmental nature of arcjet systems at this power level, the exact nature of the thruster/power processor interface was not quantified. Output regulation and current ripple requirements of 1 and 20 percent respectively, as well as starting techniques, were derived from the characteristics of the 2 kW system but an open circuit voltage in excess of 175 V was specified. Arcjet integration tests were performed, resulting in successful starts and stable arcjet operation at power levels as low as 240 W with simulated hydrazine propellants.

Hamley, John A.↗
NASA NTRS1992

Software For Computing Selected Functions

Technical memorandum presents collection of software packages in Ada implementing mathematical functions used in science and engineering. Provides programmer with function support in Pascal and FORTRAN, plus support for extended-precision arithmetic and complex arithmetic. Valuable for testing new computers, writing computer code, or developing new computer integrated circuits.

Grant, David C.↗
NASA NTRS1991

Intelligent structures technology

Viewgraphs on intelligent structures technology are presented. Topics covered include: embedding electronics; electrical and mechanical compatibility; integrated circuit chip packaged for embedding; embedding devices within composite structures; test of embedded circuit in G/E coupon; temperature/humidity/bias test; single-chip microcomputer control experiment; and structural shape determination.

Crawley, Edward F.↗
NASA NTRS2006

MMIC Power Amplifier Puts Out 40 mW From 75 to 110 GHz

A three-stage monolithic microwave integrated circuit (MMIC) W-band amplifier has been constructed and tested in a continuing effort to develop amplifiers as well as oscillators, frequency multipliers, and mixers capable of operating over wide frequency bands that extend above 100 GHz. There are numerous potential uses for MMICs like these in scientific instruments, radar systems, communication systems, and test equipment operating in this frequency range.

Samoska, Lorene↗
NASA NTRS1993

Testing self-timed circuits using scan paths

Testing is an essential part of any digital system design and one that can be made much easier if testing is considered during the design process rather than after the system is complete. There are a number of techniques for integrating testability into system design, but many of these traditional testing methods used for synchronous circuits are not directly applicable to non-clocked asynchronous circuits. As a result, many asynchronous circuits do not employ design for testability techniques. A method of using the familiar model of scan paths modified to test self-timed systems are presented. Specifically, circuits designed using a library of self-timed modules to assemble systems with two-phase transition control and bundled data paths are considered. The method involves modifying these self-timed modules such that circuits designed from them have a built-in scan path.

Khoche, Ajay↗
NASA NTRS1984

Designing a 25-kilowatt high frequency series resonant

The feasibility of processing 25 kW of power with a single, transistorized, 20 kHz, series resonant converter stage has been demonstrated by the successful design, development, fabrication, and testing of such a device. It employs four Westinghouse D7ST transistors in a full-bridge configuration and operates from a 250-to-350-Vdc input bus. The unit has an overall worst-case efficiency of 93.5% at its full rated output of 1000 V and 25 A dc. A solid-state dc input circuit breaker and output-transient-current limiters are included in and integrated into the design. Circuit details of the converter are presented along with test data.

Robson, R. R.↗
NASA NTRS1988

Characterization of a 30-GHz IMPATT solid state amplifier

Described are the characterization and testing of a 20 W solid state amplifier operating in the Ka band to be used in low cost experimental ground terminals. The amplifier was developed by the TRW Electronic Systems Group under NASA Contract NAS3-23266 as a proof-of-concept (POC) device in support of the Advanced Communications Technology Satellite (ACTS) program. Additional goals were development of high-power IMPATT devices and circulators, and multistage diode circuits, which are an integral part of the amplifier. The amplifier underwent acceptance testing at the NASA Lewis Research Center, Cleveland, Ohio. Characteristics measured include the output power of 42 dB m, gain of 30 dB, an injection-locking RF bandwidth of 260 MHz, and an overall direct current-to-radiofrequency (dc-to-RF) efficiency of 6.7 percent.

Wald, Lawrence W.↗
NASA NTRS2012

RESOLVE Project

The RESOLVE project is a lunar prospecting mission whose primary goal is to characterize water and other volatiles in lunar regolith. The Lunar Advanced Volatiles Analysis (LAVA) subsystem is comprised of a fluid subsystem that transports flow to the gas chromatograph- mass spectrometer (GC-MS) instruments that characterize volatiles and the Water Droplet Demonstration (WDD) that will capture and display water condensation in the gas stream. The LAVA Engineering Test Unit (ETU) is undergoing risk reduction testing this summer and fall within a vacuum chamber to understand and characterize C!Jmponent and integrated system performance. Ray will be assisting with component testing of line heaters, printed circuit heaters, pressure transducers, temperature sensors, regulators, and valves in atmospheric and vacuum environments. He will be developing procedures to guide these tests and test reports to analyze and draw conclusions from the data. In addition, he will gain experience with preparing a vacuum chamber with fluid and electrical connections. Further testing will include integrated testing of the fluid subsystem with the gas supply system, near-infrared spectrometer, WDD, Sample Delivery System, and GC-MS in the vacuum chamber. This testing will provide hands-on exposure to a flight forward spaceflight subsystem, the processes associated with testing equipment in a vacuum chamber, and experience working in a laboratory setting. Examples of specific analysis Ray will conduct include: pneumatic analysis to calculate the WOO's efficiency at extracting water vapor from the gas stream to form condensation; thermal analysis of the conduction and radiation along a line connecting two thermal masses; and proportional-integral-derivative (PID) heater control analysis. In this Research and Technology environment, Ray will be asked to problem solve real-time as issues arise. Since LAVA is a scientific subsystem, Ray will be utilizing his chemical engineering background to operate the near-infrared spectrometer and GC-MS instruments during ETU testing. Ray will be working with Modified Commercial off the Shelf (MCOTS) instruments and characterizing their analytical behavior for optimization. Ray will be offered the opportunity to suggest testing modifications or configuration changes at any time to improve the experimental effectiveness. He will gain many skills needed for working in a technical team setting requiring flexibility and critical thinking.

Parker, Ray O.↗
NASA NTRS1983

Tests on Double Layer Metalization

28 page report describes experiments in fabrication of integrated circuits with double-layer metalization. Double-layer metalization requires much less silicon "real estate" and allows more flexibility in placement of circuit elements than does single-layer metalization.

Woo, D. S.↗
NASA NTRS1993

Microelectronic Chips For Radiation-Dose Tests

Custom-made single-chip complementary metal-oxide semiconductor (CMOS) integrated circuit designed to reveal effects of ionizing radiation on itself and similar integrated circuits. Potential terrestrial use: safety-oriented monitoring of ionizing radiation at nuclear powerplants, nuclear-waste sites, and the like.

Buehler, Martin G.↗
NASA NTRS2003

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

infrared↗
NASA NTRS1991

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗