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At least 235 records · Page 13

Programmable Thermostat Module Upgrade for the Multi-Purpose Logistics Module

The STS-121/ULF1.1 mission was the maiden flight of the Programmable Thermostat Module (PTM) system used to control the 28 V shell heaters on the Multi-Purpose Logistics Module (MPLM). These PTMs, in conjunction with a Data Recorder Module (DRM), provide continuous closed loop temperature control and data recording of MPLM on-orbit heater operations. This paper will discuss the hardware design, development, test and verification (DDT&V) activities performed at the Marshall Space Flight Center (MSFC) as well as the operational implementation and mission performance.

Clark, Dallas↗

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.↗

Programmable Thermostat Module Upgrade for the Multipurpose Logistics Module

The STS-121/ULF 1.1 mission was the maiden flight of the programmable thermostat module (PTM) system used to control the 28 V shell heaters on the multi-purpose logistics module (MPLM). These PTMs, in conjunction with a data recorder module (DRM), provide continuous closed loop temperature control and data recording of MPLM on-orbit heater operations. This Technical Memorandum discusses the hardware design, development, test, and verification (DDT&V) activities performed at the Marshall Space Flight Center as well as the operational implementation and mission performance.

Clark, D. W.↗

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

single event effects↗

Compact programmable photonic variable delay devices

Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm.sup.2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

Yao, X. Steve↗

High Contrast Programmable Field Masks for JWST NIRSpec

Microshutter arrays are one of the novel technologies developed for the James Webb Space Telescope (JWST). It will allow Near Infrared Spectrometer (NIRSpec) to acquire spectra of hundreds of objects simultaneously therefore increasing its efficiency tremendously. We have developed these programmable arrays that are based on Micro-Electro Mechanical Structures (MEMS) technology. The arrays are 2D addressable masks that can operate in cryogenic environment of JWST. Since the primary JWST science requires acquisition of spectra of extremely faint objects, it is important to provide very high contrast of the open to closed shutters. This high contrast is necessary to eliminate any possible contamination and confusion in the acquired spectra by unwanted objects. We have developed and built a test system for the microshutter array functional and optical characterization. This system is capable of measuring the contrast of the microshutter array both in visible and infrared light of the NIRSpec wavelength range while the arrays are in their working cryogenic environment. We have measured contrast ratio of several microshutter arrays and demonstrated that they satisfy and in many cases far exceed the NIRSpec contrast requirement value of 2000.

Kutyrev, Alexander S.↗

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

global optimization↗

Programmable Low-Voltage Circuit Breaker and Tester

An instrumentation system that would comprise a remotely controllable and programmable low-voltage circuit breaker plus several electric-circuit-testing subsystems has been conceived, originally for use aboard a spacecraft during all phases of operation from pre-launch testing through launch, ascent, orbit, descent, and landing. The system could also be adapted to similar use aboard aircraft. In comparison with remotely controllable circuit breakers heretofore commercially available, this system would be smaller, less massive, and capable of performing more functions, as needed for aerospace applications.

Greenfield, Terry↗

Systems and methods for detecting a failure event in a field programmable gate array

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Ng, Tak-Kwong↗

Universal programmable logic gate and routing method

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Fijany, Amir↗

The Evolution of Gas in Protoplanetary Systems: The Herschel GASPS Open Time Key Programme

The Gas in Protoplanetary Systems (GASPS) Open Time Key Programme for the Herschel Space Observatory will be the first extensive, systematic survey of gas in circumstellar disks over the critical transition from gas-rich protoplanetary through to gas-poor debris. The brightest spectral lines from disks lie in the far-infrared and arise from radii spanning roughly 10 to 100 AU, where giant planets are expected to form. Herschel is uniquely able to observe this wavelength regime with the sensitivity to allow a large scale survey. We will execute a 2-phase study using the PACS instrument. Phase I is a spectroscopic survey about 250 young stars for fine structure emission lines of [CII] (at 157 microns) and [OI] (at 63 microns). In Phase II, the brightest sources will be followed up with additional PACS spectroscopy ([OI] at 145 microns and some rotational lines of water). We expect that the gas mass sensitivity will be more than an order of magnitude lower than that achieved by ISO and Spitzer or expected for SOFIA. We will also measure the dust continuum to an equivalent mass sensitivity. We will observe several nearby clusters with ages from 1 to 30 Myr, encompassing a wide range of disk masses and stellar luminosities. The sample covers disk evolution from protoplanetary disks through to young debris disks, i.e. the main epoch of planet formation. With this extensive dataset, the GASPS project will: 1) trace gas and dust in the planet formation region across a large multivariate parameter space, 2) provide the first definitive measurement of the gas dissipation timescale in disks, 3) elucidate the evolutionary link between protoplanetary and debris disks, 4) investigate water abundances in the planetforming regions of disks, and 5) provide a huge database of disk observations and models with long-lasting legacy value for follow-up studies.

Roberge, A.↗

The Herschel DUNES Open Time Key Programme

We will use the unique photometric capabilities provided by Herschel to perform a deep and systematic survey for faint, cold debris disks around nearby stars. Our sensitivity-limited Open Time Key Programme (OTKP) aims at finding and characterizing faint extrasolar analogues to the Edgeworth-Kuiper Belt (EKB) in an unbiased, statistically significant sample of nearby FGK main-sequence stars. Our target set spans a broad range of stellar ages (from 0.1 to 10 Gyr) and is volume-limited (distances < 20 pc). All stars with known extrasolar planets within this distance are included; additionally, some M- and A-type stars will be observed in collaboration with the Herschel DEBRIS OTKP, so that the entire sample covers a decade in stellar mass, from 0.2 to 2 solar masses. We will perform PACS and SPIRE photometric observations covering the wavelength range from 70 to 500 microns. The PACS observations at 100 microns have been designed to detect the stellar photospheres down to the confusion limit with a signal-to-noise ratio > 5. The observations in the other Herschel bands will allow us to characterize, model, and constrain the disks. As a result, it will be possible for us to reach fractional dust luminosities of a few times 10-7, close to the EKB level in the Solar System. This will provide an unprecedented lower limit to the fractional abundance of planetesimal systems and allow us to assess the presence of giant planets, which would play dynamical roles similar to those played by Jupiter and Neptune in the Solar System. The proposed observations will provide new and unique evidence for the presence of mature planetary systems in the solar neighbourhood and, in turn, will address the universality of planet/planetary system formation in disks around young stars.

Danchi, William C.↗

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Ng, Tak-kwong↗

EP/TOMS Science Data Processing Programmer's Guide. Version 1.9

This EP/TOMS Programmer's Guide provides detailed information concerning the data, software, operations, and maintenance of the EP/TOMS Science Data Processing System. This system was developed for the NASA Goddard Space Flight Center (GSFC), Laboratory for Atmospheres, Atmospheric Chemistry Branch (Code 916) by SSAI. The description of the EP/TOMS Science Data Processing System starts with an overall system perspective (Section 3). A description of all data files ingested, stored, and/or produced follows in Section 4. Detailed descriptions of each major software subsystem are in Section 5. Section 6 presents processing procedures. Section 7 presents maintenance procedures. Procedures for updating this document are included in Section 7.

Source record↗

DSP/FPGA Design for a High-Speed Programmable S-Band Space Transceiver

Traditional command uplink receivers are very limited in performance capability, take a long time to acquire, cannot operate on both uplink bands (NASA & AFSCN), and only support low-rate communications. As a result, transceivers end up on many programs critical paths, even though they should be a standard purchased spacecraft subsystem. Also, many missions are impacted by the low effective uplink throughput. In order to tackle these challenges, a transceiver was developed that will provide on-site frequency agility, support of high uplink rates, and operation on both NASA and AFSCN frequency bands. The device is a low-power, high-reliability, and high-performance digital signal processing (DSP) demodulator for an on-orbit programmable command receiver.

Janicik, Jeffrey↗

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Straka, Bartholomew↗