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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A tunable level, phase change material-based metasurface near IR optical filter on a transmissive doped silicon-on-insulator platform is demonstrated. This type of filter is non-volatile, non-mechanical, with switching being enabled by Joule heating via current pulses.
A gel electrolyte composite containing a nonvolatile electrolyte and a zwitterionic polymer scaffold in which the non-volatile electrolyte is a non-lithium-containing ionic liquid, a sodium-containing ionic liquid, or a lithium-containing ionic liquid and the zwitterionic polymer scaffold is formed from one or more zwitterionic monomers only or both one or more zwitterionic monomers and one or more non-zwitterionic monomers. The zwitterionic polymer scaffold contains 8 mol % or higher of zwitterions relative to the total content of the gel electrolyte composite when the nonvolatile electrolyte is a non-lithium-containing ionic liquid, and contains 1 mol % or higher of zwitterions relative to the total content of the gel electrolyte composite when the nonvolatile electrolyte is a sodium-containing ionic liquid or a lithium-containing ionic liquid. Also disclosed are a method of preparing the above-described gel electrolyte composite and an electrochemical energy storage device containing same.
Persistent photoconductivity and optoelectronic synaptic behavior are demonstrated in solution-processed mesoscopic α-phase vanadium pentoxide (V 2 O 5 ) thin films. First-principles simulations coupled with the two-site Holstein polaron hopping model show that vacancies at the terminal oxygen position lead to long recombination times because photoexcited electrons and holes reside on different layers separated by the van der Waals gap, forming a weakly coupled interlayer exciton polaron. Mid-gap polaronic states also significantly broaden the photoresponse of the films to span across visible and infrared wavelengths. By controlling the amplitude/intensity, duration, and/or number of optical pulses, tunable optoelectronic memory functions, such as short-term and long-term plasticity, are experimentally established in V 2 O 5 -based optoelectronic synapses. Furthermore, device fabrication was extended to mechanically flexible ultrathin glass substrates. Flexible optoelectronic synapses maintained high performance after 150 bending cycles.
Abstract Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute‐in‐memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute‐unit to memory, known as the von Neumann bottleneck. At its heart is a cross‐bar architecture with nodal non‐volatile‐memory elements that performs an analog multiply‐and‐accumulate operation, enabling the matrix‐vector‐multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system‐level characteristics and chip performance, including speed, power, and classification accuracy. With an over‐arching co‐design viewpoint, this review assesses the use of cross‐bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non‐volatile memory materials will need to demonstrate for a successful CIM technology.
In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
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This paper describes a case study quantifying reliability and endurance results of two FRAM nonvolatile memories.
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The objective of this task was to critically assess the potential of the concept of.
Conducting-tip atomic force microscopy (AFM)has been used to electronically probe silicon nanocrystals on an insulating substrate.
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We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.
We show heavy ion test results of a commercial production-level ReRAM. The memory array is robust to bit upsets. However the ReRAM system is vulnerable to SEFI.
We investigated the heavy ion SEE characteristics of an EEPROM based on CBRAM technology. SEFI is the dominant type of SEE for each operating mode (standby, read-only, write/read). We also observed single bit upsets in the CBRAM cell, during write/read tests. the SEULET threshold is between 10 and 20 MeV * sq cm/mg, with an upper fluence limit of 3 × 10(exp 6) cm(exp -2) at 10 MeV * sq cm/mg. In the stand by mode, the CBRAM array appears immune to bit upsets.
One time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.