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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Active Pixel Sensors: Are CCD's Dinosaurs?

Charge-coupled devices (CCD's) are presently the technology of choice for most imaging applications. In the 23 years since their invention in 1970, they have evolved to a sophisticated level of performance. However, as with all technologies, we can be certain that they will be supplanted someday. In this paper, the Active Pixel Sensor (APS) technology is explored as a possible successor to the CCD. An active pixel is defined as a detector array technology that has at least one active transistor within the pixel unit cell. The APS eliminates the need for nearly perfect charge transfer -- the Achilles' heel of CCDs. This perfect charge transfer makes CCD's radiation 'soft,' difficult to use under low light conditions, difficult to manufacture in large array sizes, difficult to integrate with on-chip electronics, difficult to use at low temperatures, difficult to use at high frame rates, and difficult to manufacture in non-silicon materials that extend wavelength response.

Fossum, Eric R.↗
NASA NTRS2001

Development of Low-Noise High Value Chromium Silicide Resistors for Cryogenic Detector Applications

Extremely high sensitivity detectors, such as silicon bolometers are required in many NASA missions for detection of photons from the x-ray to the far infrared regions. Typically, these detectors are cooled to well below the liquid helium (LHe) temperature (4.2 K) to achieve the maximum detection performance. As photoconductors, they are generally operated with a load resistor and a pre-set bias voltage, which is then coupled to the input gate of a source-follower Field Effect Transistor (FET) circuit. It is imperative that the detector system signal to noise performance be limited by the noise of the detector and not by the noise of the external components. The load resistor value is selected to optimize the detector performance. These two criteria tend to be contradictory in that these detectors require load resistors in the hundreds of megaohms, which leads to a higher Johnson noise. Additionally, the physical size of the resistor must be small for device integration as required by such missions as the NASA High Resolution Airborne Wide-Band Camera (HAWC) instrument and the Submillimeter High Angular Resolution Camera (SHARC) for the Caltech Submillimeter Observatory (CSO). We have designed, fabricated and characterized thin film resistors using a CrSi/TiW/Al metal system on optical quality quartz substrates. The resistor values range from 100 megaohms to over 650 megaohms and are Johnson noise limited at LHe temperatures. The resistor film is sputtered with a sheet resistance ranging from 300 ohms to 1600 ohms and the processing sequence developed for these devices allows for chemically fine tuning the sheet resistance in-situ. The wafer fabrication process was of sufficiently high yield (>80%) providing clusters of good resistors for integrated multiple detector channels, a very important feature in the assembly of these two instruments.

Jhabvala, Murzy↗
NASA NTRSDate not supplied

Processing Choices for Achieving Long Term IC Operation at 500 °C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

silicon carbide↗
NASA NTRS1972

Methods of measurement for semiconductor materials, process control, and devices

Significant accomplishments include development of a procedure to correct for the substantial differences of transistor delay time as measured with different instruments or with the same instrument at different frequencies; association of infrared response spectra of poor quality germanium gamma ray detectors with spectra of detectors fabricated from portions of a good crystal that had been degraded in known ways; and confirmation of the excellent quality and cosmetic appearance of ultrasonic bonds made with aluminum ribbon wire. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon, development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

Bullis, W. M.↗
NASA NTRS1991

Development of silicon carbide semiconductor devices for high temperature applications

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Matus, Lawrence G.↗
NASA NTRS1993

Chemical Vapor Deposition Of Silicon Carbide

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Powell, J. Anthony↗
NASA NTRS1977

Adaptation of ion beam technology to microfabrication of solid state devices and transducers

It was found that ion beam texturing of silicon surfaces can be used to increase the effective surface area of MOS capacitors. There is, however, a problem with low dielectric breakdown. Preliminary work was begun on the fabrication of ion implanted resistors on textured surfaces and the potential improvement of wire bond strength by bonding to a textured surface. In the area of ion beam sputtering, the techniques for sputtering PVC were developed. A PVC target containing valinomycin was used to sputter an ion selective membrane on a field effect transistor to form a potassium ion sensor.

Topich, J. A.↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRS1999

Analyses of Transistor Punchthrough Failures

The failure of two transistors in the Altitude Switch Assembly for the Solid Rocket Booster followed by two additional failures a year later presented a challenge to failure analysts. These devices had successfully worked for many years on numerous missions. There was no history of failures with this type of device. Extensive checks of the test procedures gave no indication for a source of the cause. The devices were manufactured more than twenty years ago and failure information on this lot date code was not readily available. External visual exam, radiography, PEID, and leak testing were performed with nominal results Electrical testing indicated nearly identical base-emitter and base-collector characteristics (both forward and reverse) with a low resistance short emitter to collector. These characteristics are indicative of a classic failure mechanism called punchthrough. In failure analysis punchthrough refers to an condition where a relatively low voltage pulse causes the device to conduct very hard producing localized areas of thermal runaway or "hot spots". At one or more of these hot spots, the excessive currents melt the silicon. Heavily doped emitter material diffuses through the base region to the collector forming a diffusion pipe shorting the emitter to base to collector. Upon cooling, an alloy junction forms between the pipe and the base region. Generally, the hot spot (punch-through site) is under the bond and no surface artifact is visible. The devices were delidded and the internal structures were examined microscopically. The gold emitter lead was melted on one device, but others had anomalies in the metallization around the in-tact emitter bonds. The SEM examination confirmed some anomalies to be cosmetic defects while other anomalies were artifacts of the punchthrough site. Subsequent to these analyses, the contractor determined that some irregular testing procedures occurred at the time of the failures heretofore unreported. These testing irregularities involved the use of a breakout box and were the likely cause of the failures. There was no evidence to suggest a generic failure mechanism was responsible for the failure of these transistors.

Nicolas, David P.↗
NASA NTRS2008

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Hunter, Gary W.↗
NASA NTRS2008

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Hunter, Gary W.↗
NASA NTRS2011

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Hunter, Gary W.↗
NASA NTRS1992

A VLSI implementation of DCT using pass transistor technology

A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

Kamath, S.↗
NASA NTRS2009

NASA Tech Briefs, January 2009

Tech Briefs are short announcements of innovations originating from research and development activities of the National Aeronautics and Space Administration. They emphasize information considered likely to be transferable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. Topics covered include: The Radio Frequency Health Node Wireless Sensor System; Effects of Temperature on Polymer/Carbon Chemical Sensors; Small CO2 Sensors Operate at Lower Temperature; Tele-Supervised Adaptive Ocean Sensor Fleet; Synthesis of Submillimeter Radiation for Spectroscopy; 100-GHz Phase Switch/Mixer Containing a Slot-Line Transition; Generating Ka-Band Signals Using an X-Band Vector Modulator; SiC Optically Modulated Field-Effect Transistor; Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions; Metrology System for a Large, Somewhat Flexible Telescope; Economical Implementation of a Filter Engine in an FPGA; Improved Joining of Metal Components to Composite Structures; Machined Titanium Heat-Pipe Wick Structure; Gadolinia-Doped Ceria Cathodes for Electrolysis of CO2; Utilizing Ocean Thermal Energy in a Submarine Robot; Fuel-Cell Power Systems Incorporating Mg-Based H2 Generators; Alternative OTEC Scheme for a Submarine Robot; Sensitive, Rapid Detection of Bacterial Spores; Adenosine Monophosphate-Based Detection of Bacterial Spores; Silicon Microleaks for Inlets of Mass Spectrometers; CGH Figure Testing of Aspherical Mirrors in Cold Vacuums; Series-Coupled Pairs of Silica Microresonators; Precise Stabilization of the Optical Frequency of WGMRs; Formation Flying of Components of a Large Space Telescope; Laser Metrology Heterodyne Phase-Locked Loop; Spatial Modulation Improves Performance in CTIS; High-Performance Algorithm for Solving the Diagnosis Problem; Truncation Depth Rule-of-Thumb for Convolutional Codes; Efficient Method for Optimizing Placement of Sensors.

Source record↗
NASA NTRS1994

Silicon device performance measurements to support temperature range enhancement

Silicon based power devices can be used at 200 C. The device measurements made during this program show a predictable shift in device parameters with increasing temperature. No catastrophic or abrupt changes occurred in the parameters over the temperature range. As expected, the most dramatic change was the increase in leakage currents with increasing temperature. At 200 C the leakage current was in the milliAmp range but was still several orders of magnitude lower than the on-state current capabilities of the devices under test. This increase must be considered in the design of circuits using power transistors at elevated temperature. Three circuit topologies have been prototyped using MOSFET's and IGBT's. The circuits were designed using zero current or zero voltage switching techniques to eliminate or minimize hard switching of the power transistors. These circuits have functioned properly over the temperature range. One thousand hour life data have been collected for two power supplies with no failures and no significant change in operating efficiency. While additional reliability testing should be conducted, the feasibility of designing soft switched circuits for operation at 200 C has been successfully demonstrated.

Bromstead, James↗
NASA NTRS2018

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗
NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗
NASA NTRS1979

Bandgap narrowing in moderately to heavily doped silicon

A theoretical model of bandgap narrowing in silicon at high doping levels has been developed. The model takes into account the electrostatic energy of interaction between a minority carrier and the majority carriers surrounding it, which reduces the thermal energy necessary for creation of an electron-hole pair. A pair energy similar to the excitonic binding energy of bound electron-hole pairs in insulators is obtained. Theoretical results are in excellent agreement with experimental results in the doping range from 3 times 10 to the 17th to 1.5 times 10 to the 20th/cu cm at room temperature. These results indicate that at high injection levels such as a transistor biased into the conductivity-modulation regime or a solar cell whose surface is established by ion implantation into an oxide layer, the bandgap narrowing is determined by the injected carrier concentration rather than by the doping level.

Lanyon, H. P. D.↗