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This presentation on Field Programmable Gate Array (FPGA) Devices will include challenges for critical applications and space radiation environments, Single Event Upsets (SEUs) and FPGA configuration, Single Event Upsets (SEUs) and FPGA data paths, and fail-safe strategies for critical applications.
The main purpose of this guideline is to document the current understanding of the effort and tradeoffs involved in using SRAM-based FPGAs with maximum achievable upset tolerance. This guideline summarizes the different testing strategies to be considered when assessing the SEE tolerance of SRAM-based FPGAs. For critical applications, in-beam testing of flight designs is strongly recommended in order to verify that the upset mitigation is working as well as the designer intended. At present, there are four manufacturers (Actel, Xilinx, Atmel, and Aeroflex) offering six FPGA types to the military market (i.e., some military spec screening and testing are specified) and four device types to the aerospace application market, which indicates that the manufacturers have added radiation parameter specifications. There is also a Honeywell and BAE Systems device that has been under development for several years, but it does not appear to be available yet; inquiries to Honeywell’s military/aerospace marketing arm on this product have been unanswered.
This paper discusses single-event upset in memories and microprocessors, along with the mechanisms that cause SEU effects.
The SEU/SRAM is a 4-kbit Static Random Access Memory (SRAM) designed to detect Single-Event Upsets (SEUs) produced by high energy particles. This device was used to determine the distribution in the memory cell spontaneous flip potential.
Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.
This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.
This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.
We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
We present a framework for evaluating complex digital systems targeted for harsh radiation environments such as space. Focus is limited to analyzing the single event upset (SEU) susceptibility of designs implemented inside Field Programmable Gate Array (FPGA) devices. Tradeoffs are provided between application-specific versus test-specific test structures.
Single event upset (SEU) analysis of complex systems is challenging. Currently, system SEU analysis is performed by component level partitioning and then either: the most dominant SEU cross-sections (SEUs) are used in system error rate calculations; or the partition SEUs are summed to eventually obtain a system error rate. In many cases, system error rates are overestimated because these methods generally overlook system level derating factors. The problem with overestimating is that it can cause overdesign and consequently negatively affect the following: cost, schedule, functionality, and validation/verification. The scope of this presentation is to discuss the risks involved with our current scheme of SEU analysis for complex systems; and to provide alternative methods for improvement.
The Analog Devices ADV212 was initially tested for single event effects (SEE) at the Texas AM University Cyclotron Facility (TAMU) in July of 2013. Testing revealed a sensitivity to device hang-ups classified as single event functional interrupts (SEFI), soft data errors classified as single event upsets (SEU), and, of particular concern, single event latch-ups (SEL). All error types occurred so frequently as to make accurate measurements of the exposure time, and thus total particle fluence, challenging. To mitigate some of the risk posed by single event latch-ups, circuitry was added to the electrical design to detect a high current event and automatically recycle power and reboot the device. An additional heavy-ion test was scheduled to validate the operation of the recovery circuitry and the continuing functionality of the ADV212 after a substantial number of latch-up events. As a secondary goal, more precise data would be gathered by an improved test method, described in this test report.
We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data to improve system survivability prediction.
The Analog Devices ADXL354 3-AXIS MEMS accelerometer was tested for single-event effects, both destructive and non-destructive. The device was characterized for single-event upset (SEU) sensitivity and evaluated for any possibility of single-event latchup (SEL), single-event dielectric rupture (SEDR) and single-event functional interrupts (SEFI). Single-event transient (SET) response was also monitored.
Experimental measurements of the currents in pyro-activation circuits show that a structure current is generated during the pyro-activation process. This current is a transient current and is an intense source of electromagnetic interference. Analysis has indicated that the noise voltage induced on candidate victim circuits is sufficient to cause circuit upset and/or latchup. A survey of flight anomaly records has also correlated the occurrence of anomalies with the pyro-activation process. Detailed analyses, taking the spacecraft cabling configuration and circuit sensitivities into account, have shown that the structure current induced noise voltage could definitely be the cause of the anomalies. The threat of the structure current due to pyro-activation can be alleviated by isolating the pyro-activation circuit from ground and by proper arrangement of the cables in sensitive circuits.
Single-event upsets are observed in a 72-layer 3D NAND flash memory operated in single-level cell mode after low-energy proton (500 keV-1.2 MeV) and heavy ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of low energy protons within the memory stack, and Monte Carlo simulations are correlated with the experimental data. Direct ionization by low-energy protons is identified by three-dimensional data analysis and the energy dependence of device sensitive cross-section. Heavy ion data is also presented for comparison.
Symmetrical, cruciform key has end tabs which bend up to lock tubine rotor blades against axial displacement. The key locks without introducing aerodynamic resistance or upsetting rotor balance.
Upset forging tests on aluminum and titanium alloys and maraging steel using high temperature dies
An approach to stabilizing control systems is presented which structures controllers like passive mechanical systems. The controller is visualized as a structural part with a passive behavior similar to springs, dashpots, and masses. If such a controller is connected by a proper feedback arrangement, then a passive mechanical plant cannot upset stability, regardless of masses, resonances, and three-dimensional coupling. The concept of resonance-inert stabilization is explained by structuring the controller of a simple feedback loop. Reactive functions, connections, and matrices are defined and used in the stabilization concept. The realization of a possible Skylab control system is discussed and compared with the present design. This example demonstrates the applicability to three-dimensional problems with lagging controllers.