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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Quality assurance and quality control of the $26~\text {m}^2$ SiPM production for the DarkSide-20k dark matter experiment

DarkSide-20k is a novel liquid argon dark matter detector currently under construction at the Laboratori Nazionali del Gran Sasso (LNGS) of the Istituto Nazionale di Fisica Nucleare (INFN) that will push the sensitivity for Weakly Interacting Massive Particle (WIMP) detection into the neutrino fog. The core of the apparatus is a dual-phase Time Projection Chamber (TPC), filled with 50 tonnes of low radioactivity underground argon (UAr) acting as the WIMP target. NUV-HD-cryo Silicon Photomultipliers (SiPM)s designed by Fondazione Bruno Kessler (FBK) (Trento, Italy) were selected as the photon sensors covering two $10.5~\text {m}^2$ Optical Planes, one at each end of the TPC, and a total of $5~\text {m}^2$ photosensitive surface for the liquid argon veto detectors. This paper describes the Quality Assurance and Quality Control (QA/QC) plan and procedures accompanying the production of FBK NUV-HD-cryo SiPM wafers manufactured by LFoundry s.r.l. (Avezzano, AQ, Italy). SiPM characteristics are measured at 77 K at the wafer level with a custom-designed probe station. As of March 2025, 1314 of the 1400 production wafers (94% of the total) for DarkSide-20k were tested. The wafer yield is $93.2\pm 2.5$%, which exceeds the 80% specification defined in the original DarkSide-20k production plan.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1971

Shielding method for polycrystalline and epitaxy growths

Technique prevents silicon wafers from adhering to susceptor following silicon epitaxial deposition. Annular ring of refractory material goes around wafer during epitaxial deposit. Silicon is deposited on ring, susceptor, and portions of wafer. Ring breaks away from susceptor and wafer and no silicon undergrowth occurs.

Bue, J. L.↗
NASA NTRS1976

Economic analysis of low cost silicon sheet produced from Czochralski grown material

This study shows that the lower limits for manufacturing add-on costs to convert polysilicon to wafers is in the range of $22 to $26/sq m with the cost about equally divided between the crystal growth and wafering processes. However, the $22 to $26/sq m cost limit should be viewed as an asymptote since it is based on multicharge or continuous growth configurations, solidification rates in excess of 2 Kg/hr, multiblade wafering and a slice plus kerf of .045 cm. It should also be emphasized that the results of this study are based on as-sawn wafers, 100% yields (growth and slicing) and no profit. To the first approximation, the limiting cost factors are crucible material and furnace parts for growth and blade material and slurry for slicing.

Koliwad, K. M.↗
NASA NTRS1978

Effect of multiblade slurry saw induced damage on silicon solar cells

A correlation between the optimum etch loss and the depth of damage is established using wafers produced by the Multiblade Slurry (MBS) and the Internal Diameter (ID) saws. The observations are based on the measurement of the performance of solar cells fabricated on these wafers. Sample preparation and test results are described and the following conclusions are made: (1) the amount of silicon removal necessary for optimum solar cell performance coincides with the depth of saw-induced damage; (2) optimization of cell performance is not affected by the method of silicon removal; (3) sawing conditions should be optimized to minimize the extent of saw-induced damage; (4) the MBS saw is found to induce damage to a lesser extent; (5) since the extent of damage in MBS-sawn wafers is in the limit of etch loss required in texture etching, it is possible to achieve optimum improvement in cell performance by merely texture etching the surface of as-sawn wafers.

Daud, T.↗
NASA NTRS1980

Development and fabrication of a solar cell junction processing system

Experiments were completed which indicate that single-pulse, liquid-phase epitaxial regrowth is the optimum technique for pulsed electron beam annealing of ion implantation damage in silicon wafers. An electron beam which covers the entire area of the wafer was chosen for the solar cell processor. Beam control experiments to improve beam propagation and to test the concept of partial space charge and current neutralization were initiated. The electrical parameters of the pulsed electron beam subsystem were chosen on the basis of computer calculations and past experience in pulsed electron accelerator design and operation. The pulser, designated SPI-PULSE 7000, is designed to anneal 10 cm diameter silicon wafers at a rate of 30 per minute. The preliminary design of the major elements of the SPI-PULSE 7000 was completed, and the detailed design of many of the components begun. These elements include a capacitive energy store and charging system, an electron accelerator, a beam control system, a wafer handling system and pressure and vacuum assemblies.

Halvason, W.↗
NASA NTRS1981

X-ray topography study of complex silicon microcircuits

The correlation between the yield of silicon microcircuits wafers versus defects observed in X-ray topographs produced by a high speed curved wafer X-ray topographic camera was investigated. Most of the topographs were made after final wafer probe. Results indicated that most high volume silicon wafer processing does not need X-ray topography as a routine process control. It is further indicated that in changing any existing process or developing a new process the technique can be of significant benefit.

Parker, D. L.↗
NASA NTRS1981

Silicon solar cell process development, fabrication and analysis

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Yoo, H. I.↗
NASA NTRS1982

Design and use of multiple blade slurry sawing in a production atmosphere

The technique and uses of the multiple blade slurry (MBS) saw are considered. Multiple bands of steel are arranged in a frame and the frame is reciprocated with the steel bands to a workpiece, while simultaneously applying abrasive at the point of contact. The blades wear slots in the workpiece and progress through the piece resulting in several parts of wafers. The transition to MBA from diamond slicing is justified by savings resulting from minimized kerf losses, minimized subsurface damage, and improved surface quality off the saw. This allows wafering much closer to finished thickness specifications. The current state of the art MBS technology must be significantly improved if the low cost solar array (LSA) goals are to be attained. It is concluded that although MBS will never be the answer to every wafering requirement, the economical production of wafers to LSA project specifications will be achieved.

Lynah, F. P., Jr.↗
NASA NTRS1982

Field experience with various slicing methods

Wafer slicing using internal diameter (ID) saw, multiblade slurry (MBS) saw and multiwire slurry (MWS) saw techniques were evaluated. Wafer parameters such as bow, taper, and roughness which may not be important factors for solar cell fabrication, were considerably better for ID saw than those of the MBS and MWS saw. Analysis of add-on slicing cost indicated that machine productivity seems to be a major limiting factor for ID saw, while expendible material costs are a major factor for both MBS and MWS saw. Slicing experience indicated that the most important factors controling final wafer cost are: (1) silicon cost (wafer thickness + kerf loss); (2) add-on slicing cost, and (3) mechanical yield. There is a very strong interaction between these parameters, suggesting a necessity of optimization of these parameters.

Yoo, H. I.↗
NASA NTRS1982

Silicon solar cell process development, fabrication and analysis

For UCP Si, randomly selected wafers and wafers cut from two specific ingots were studied. For the randomly selected wafers, a moderate gettering diffusion had little effect. Moreover, an efficiency up to 14% AMI was achieved with advanced processes. For the two specific UCP ingots, ingot #5848-13C displayed severe impurity effects as shown by lower 3sc in the middle of the ingot and low CFF in the top of the ingot. Also the middle portions of this ingot responded to a series of progressively more severe gettering diffusion. Unexplained was the fact that severely gettered samples of this ingot displayed a negative light biased effect on the minority carrier diffusion length while the nongettered or moderately gettered ones had the more conventional positive light biased effect on diffusion length. On the other hand, ingot C-4-21A did not have the problem of ingot 5848-13C and behaved like to the randomly selected wafers. The top half of the ingot was shown to be slightly superior to the bottom half, but moderate gettering helped to narrow the gap.

Iles, P. A.↗
NASA NTRS1985

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Buehler, M. G.↗
NASA NTRS1987

Screening Mechanically-Defective Solar Cells

Flexure test eliminates failure-prone wafers before further processing. Probability of cracking of silicon solar cells substantially reduced by mechanical proof testing of silicon wafers before further processing, according to report. Report based on study demonstrating weak wafers eliminated by subjecting all wafers in manufacturing batch to biaxial-flexure test.

Chen, C. P.↗
NASA NTRS1992

Sub-Kelvin resistance thermometer

A device capable of accurate temperature measurement down to 0.01 K of a particular object is discussed. The device is comprised of the following: a heat sink wafer; a first conducting pad bonded near one end of the heat sink wafer; a second conducting pad bonded near the other end of the heat sink wafer; and an oblong doped semiconductor crystal such as germanium. The oblong doped semiconductor crystal has a third conducting pad bonded on its bottom surface with the oblong doped semiconductor crystal bonded to the heat sink wafer by having the fourth conducting pad bonded to the first conducting pad. A wire is bonded between the second and third conducting pads. Current and voltage wires bonded to the first and second conducting pads measure the change in resistance of the oblong doped semiconductor crystal; this indicates the temperature of the object whose temperature is to be measured.

Castles, Stephen H.↗
NASA NTRS1992

Silicon micromachined waveguides for millimeter and submillimeter wavelengths

The majority of radio receivers, transmitters, and components operating at millimeter and submillimeter wavelengths utilize rectangular waveguides in some form. However, conventional machining techniques for waveguides operating above a few hundred GHz are complicated and costly. This paper reports on the development of silicon micromachining techniques to create silicon-based waveguide circuits which can operate at millimeter and submillimeter wavelengths. As a first step, rectangular WR-10 waveguide structures have been fabricated from (110) silicon wafers using micromachining techniques. The waveguide is split along the broad wall. Each half is formed by first etching a channel completely through a wafer. Potassium hydroxide is used to etch smooth mirror-like vertical walls and LPCVD silicon nitride is used as a masking layer. This wafer is then bonded to another flat wafer using a polyimide bonding technique and diced into the U-shaped half wavelengths. Finally, a gold layer is applied to the waveguide walls. Insertion loss measurements show losses comparable to those of standard metal waveguides. It is suggested that active devices and planar circuits can be integrated with the waveguides, solving the traditional mounting problems. Potential applications in terahertz instrumentation technology are further discussed.

Yap, Markus↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS1993

Comprehensive investigation of HgCdTe metalorganic chemical vapor deposition

The principal objective of this experimental and theoretical research program was to explore the possibility of depositing high quality epitaxial CdTe and HgCdTe at very low pressures through metalorganic chemical vapor deposition (MOCVD). We explored two important aspects of this potential process: (1) the interaction of molecular flow transport and deposition in an MOCVD reactor with a commercial configuration, and (2) the kinetics of metal alkyl source gas adsorption, decomposition and desorption from the growing film surface using ultra high vacuum surface science reaction techniques. To explore the transport-reaction issue, we have developed a reaction engineering analysis of a multiple wafer-in-tube ultrahigh vacuum chemical vapor deposition (UHV/CVD) reactor which allows an estimate of wafer or substrate throughput for a reactor of fixed geometry and a given deposition chemistry with specified film thickness uniformity constraints. The model employs a description of ballistic transport and reaction based on the pseudo-steady approximation to the Boltzmann equation in the limit of pure molecular flow. The model representation takes the form of an integral equation for the flux of each reactant or intermediate species to the wafer surfaces. Expressions for the reactive sticking coefficients (RSC) for each species must be incorporated in the term which represents reemission from a wafer surface. The interactions of MOCVD precursors with Si and CdTe were investigated using temperature programmed desorption (TPD) in ultra high vacuum combined with Auger electron spectroscopy (AES). These studies revealed that diethyltellurium (DETe) and dimethylcadmium (DMCd) adsorb weakly on clean Si(100) and desorb upon heating without decomposing. These precursors adsorb both weakly and strongly on CdTe(111)A, with DMCd exhibiting the stronger interaction with the surface than DETe.

Raupp, Gregory B.↗
NASA NTRS1961

A Technique for Increasing the Sensitivity of a Solid-State Fission Probe

A small silicon p-n junction wafer, when coated with uranium 235, can be used as a compact fission probe for low power flux and power mapping. Because of the inverse relation between the magnitude of a neutron-induced fission pulse and the inherent capacitance of the detecting element (capacitance is proportional to area), the size, and hence the sensitivity, of the semiconductor detector has been limited. New developments in the field of semiconductor detectors have made it possible to fabricate large area detectors which are essentially free from the capacitance effect. However, preliminary results indicate that they are much more susceptible to radiation damage than the detectors described in this report and as such may not be suitable for flux mapping. increasing the sensitivity cannot be accomplished by simply fabricating a larger detector. It has been observed that by combining the silicon p-n junction wafers in a series configuration the capacitance effect can be bypassed, and a fission probe can be made with a resultant increase in sensitivity by a factor of ten while sustaining only a minor decrease in pulse height. Analysis further indicates that for n silicon wafers in series, if n(C(sub i)) + C(sub c)/C(sub b) less than 0.1 where C(sub i) and C(sub c) are the preamplifier input and cable capacitances, respectively, and C(sub b) is the junction capacitance of a single silicon wafer, there should be no substantial reduction in pulse height due to series circuitry.

Steinberg, Robert↗
NASA NTRS2001

Piezoelectric Vibrational and Acoustic Alert for a Personal Communication Device

An alert apparatus for a personal communication device includes a mechanically prestressed piezoelectric wafer positioned within the personal communication device and an alternating voltage input line coupled at two points of the wafer where polarity is recognized. The alert apparatus also includes a variable frequency device coupled to the alternating voltage input line, operative to switch the alternating voltage on the alternating voltage input line at least between an alternating voltage having a first frequency and an alternating voltage having a second frequency. The first frequency is preferably sufficiently high so as to cause the wafer to vibrate at a resulting frequency that produces a sound perceptible by a human ear, and the second frequency is preferably sufficiently low so as to cause the wafer to vibrate at a resulting frequency that produces a vibration readily felt by a holder of the personal communication device.

Stanley E Woodard↗