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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

Development, Implementation, and Pilot Evaluation of a Model-Driven Envelope Protection System to Mitigate the Hazard of In-Flight Ice Contamination on a Twin-Engine Commuter Aircraft

Fatal loss-of-control accidents have been directly related to in-flight airframe icing. The prototype system presented in this report directly addresses the need for real-time onboard envelope protection in icing conditions. The combination of prior information and real-time aerodynamic parameter estimations are shown to provide sufficient information for determining safe limits of the flight envelope during inflight icing encounters. The Icing Contamination Envelope Protection (ICEPro) system was designed and implemented to identify degradations in airplane performance and flying qualities resulting from ice contamination and provide safe flight-envelope cues to the pilot. The utility of the ICEPro system for mitigating a potentially hazardous icing condition was evaluated by 29 pilots using the NASA Ice Contamination Effects Flight Training Device. Results showed that real time assessment cues were effective in reducing the number of potentially hazardous upset events and in lessening exposure to loss of control following an incipient upset condition. Pilot workload with the added ICEPro displays was not measurably affected, but pilot opinion surveys showed that real time cueing greatly improved their awareness of a hazardous aircraft state. The performance of ICEPro system was further evaluated by various levels of sensor noise and atmospheric turbulence.

simulation training↗
NASA NTRS2015

Single-Event Effect Performance of a Conductive-Bridge Memory EEPROM

We investigated the heavy ion SEE characteristics of an EEPROM based on CBRAM technology. SEFI is the dominant type of SEE for each operating mode (standby, read-only, write/read). We also observed single bit upsets in the CBRAM cell, during write/read tests. the SEULET threshold is between 10 and 20 MeV * sq cm/mg, with an upper fluence limit of 3 × 10(exp 6) cm(exp -2) at 10 MeV * sq cm/mg. In the stand by mode, the CBRAM array appears immune to bit upsets.

single event effects↗
NASA NTRS2017

High-Fidelity Multi-Rotor Unmanned Aircraft System Simulation Development for Trajectory Prediction Under Off-Nominal Flight Dynamics

The NASA Unmanned Aircraft System (UAS) Traffic Management (UTM) project is conducting research to enable civilian low-altitude airspace and UAS operations. A goal of this project is to develop probabilistic methods to quantify risk during failures and off nominal flight conditions. An important part of this effort is the reliable prediction of feasible trajectories during off-nominal events such as control failure, atmospheric upsets, or navigation anomalies that can cause large deviations from the intended flight path or extreme vehicle upsets beyond the normal flight envelope. Few examples of high-fidelity modeling and prediction of off-nominal behavior for small UAS (sUAS) vehicles exist, and modeling requirements for accurately predicting flight dynamics for out-of-envelope or failure conditions are essentially undefined. In addition, the broad range of sUAS aircraft configurations already being fielded presents a significant modeling challenge, as these vehicles are often very different from one another and are likely to possess dramatically different flight dynamics and resultant trajectories and may require different modeling approaches to capture off-nominal behavior. NASA has undertaken an extensive research effort to define sUAS flight dynamics modeling requirements and develop preliminary high fidelity six degree-of-freedom (6-DOF) simulations capable of more closely predicting off-nominal flight dynamics and trajectories. This research has included a literature review of existing sUAS modeling and simulation work as well as development of experimental testing methods to measure and model key components of propulsion, airframe and control characteristics. The ultimate objective of these efforts is to develop tools to support UTM risk analyses and for the real-time prediction of off-nominal trajectories for use in the UTM Risk Assessment Framework (URAF). This paper focuses on modeling and simulation efforts for a generic quad-rotor configuration typical of many commercial vehicles in use today. An overview of relevant off-nominal multi-rotor behaviors will be presented to define modeling goals and to identify the prediction capability lacking in simplified models of multi-rotor performance. A description of recent NASA wind tunnel testing of multi-rotor propulsion and airframe components will be presented illustrating important experimental and data acquisition methods, and a description of preliminary propulsion and airframe models will be presented. Lastly, examples of predicted off-nominal flight dynamics and trajectories from the simulation will be presented.

Foster, John V.↗
NASA NTRS2018

FPGA Mitigation Strategies for Critical Applications

This presentation on Field Programmable Gate Array (FPGA) Devices will include challenges for critical applications and space radiation environments, Single Event Upsets (SEUs) and FPGA configuration, Single Event Upsets (SEUs) and FPGA data paths, and fail-safe strategies for critical applications.

Space radiation environments↗
NASA NTRS2008

Assessing and mitigating radiation effects in Xilinx FPGAs

The main purpose of this guideline is to document the current understanding of the effort and tradeoffs involved in using SRAM-based FPGAs with maximum achievable upset tolerance. This guideline summarizes the different testing strategies to be considered when assessing the SEE tolerance of SRAM-based FPGAs. For critical applications, in-beam testing of flight designs is strongly recommended in order to verify that the upset mitigation is working as well as the designer intended. At present, there are four manufacturers (Actel, Xilinx, Atmel, and Aeroflex) offering six FPGA types to the military market (i.e., some military spec screening and testing are specified) and four device types to the aerospace application market, which indicates that the manufacturers have added radiation parameter specifications. There is also a Honeywell and BAE Systems device that has been under development for several years, but it does not appear to be available yet; inquiries to Honeywell’s military/aerospace marketing arm on this product have been unanswered.

Allen, Greg↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Assessment of the Corrosion Risks to a Double Shell Tank During the Selective Removal of a Cesium-rich Supernate Layer - 20227

The Direct Feed Low Activity Waste (DF-LAW) activity will provide the initial feed to the Waste Treatment and Immobilization Plant at the Hanford Tank Farm facility. Feed preparation for DF-LAW will be carried out in multiple double shell waste tanks (DST) utilizing the Tank Side Cesium Removal (TSCR) process. Tank AP-106 will be an integral part of the TSCR process and hence key to the DFLAW activity. Prior to being utilized for this purpose, the Cs-137 concentration levels in the AP-106 supernate must be reduced significantly. The AP-106 re-purposing process manages normal waste tank addition procedures such that waste acceptance criteria objectives for Cs-137 removal are achieved. As this process was being developed, several concerns regarding tank integrity during and after repurposing of Tank AP-106, and the associated tanks (i.e., AP-102, AN-101, and AP-108), were addressed. The potential corrosion degradation mechanisms identified based on process knowledge included: general and pitting corrosion, caustic stress corrosion cracking, concentration cell corrosion, and microbiologically induced corrosion (MIC). A systematic approach was undertaken to assess the risk of corrosion during the AP-106 re-purposing process. The assessment considered the initial and present condition of the tank, the service history of the tank, the environmental conditions created in each tank during each stage of the process, process timing, and corrosion testing and modeling that approximated tank conditions. Based on this information, recommendations were provided to minimize the exposure of the tank to corrosive conditions. These recommendations included time limits for each stage of the process, staging of corrosion inhibitor solutions should process delays occur, and waste sampling with potential chemistry adjustments at defined steps in the process. Additionally, recommendations for post-process supernate chemistry adjustments and tank inspections were put forth. The greatest risk for this process occurs during the manipulation of large quantities of Columbia River water (i.e., greater than 450,000 gallons) within AP-106, the associated tanks and the supporting infrastructure (i.e., transfer line piping). This risk becomes more pronounced if there is a process upset and the tank walls remain exposed to a corrosive condition longer than intended. As long as the river water is blended into the supernate in a timely fashion, and the waste is adjusted appropriately with corrosion inhibitors, corrosion may be minimized and the final condition of the supernate in AP-106 and the associated tanks is expected to be in compliance with corrosion chemistry requirements. Contingency plans will be made to minimize the impact of a process upset. (authors)

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
NASA NTRS1993

SEU/SRAM as a Process Monitor

The SEU/SRAM is a 4-kbit Static Random Access Memory (SRAM) designed to detect Single-Event Upsets (SEUs) produced by high energy particles. This device was used to determine the distribution in the memory cell spontaneous flip potential.

distribution residual plots↗
NASA NTRS2004

IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA

Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.

single event upset (SEU)↗
NASA NTRS2006

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
NASA NTRS2010

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

error rate calculations↗
NASA NTRS2014

SEU System Analysis: Not Just the Sum of All Parts

Single event upset (SEU) analysis of complex systems is challenging. Currently, system SEU analysis is performed by component level partitioning and then either: the most dominant SEU cross-sections (SEUs) are used in system error rate calculations; or the partition SEUs are summed to eventually obtain a system error rate. In many cases, system error rates are overestimated because these methods generally overlook system level derating factors. The problem with overestimating is that it can cause overdesign and consequently negatively affect the following: cost, schedule, functionality, and validation/verification. The scope of this presentation is to discuss the risks involved with our current scheme of SEU analysis for complex systems; and to provide alternative methods for improvement.

Single Event Upset (SEU) Testing↗
NASA NTRS2017

Single Event Effect Testing of the Analog Devices ADV212

The Analog Devices ADV212 was initially tested for single event effects (SEE) at the Texas AM University Cyclotron Facility (TAMU) in July of 2013. Testing revealed a sensitivity to device hang-ups classified as single event functional interrupts (SEFI), soft data errors classified as single event upsets (SEU), and, of particular concern, single event latch-ups (SEL). All error types occurred so frequently as to make accurate measurements of the exposure time, and thus total particle fluence, challenging. To mitigate some of the risk posed by single event latch-ups, circuitry was added to the electrical design to detect a high current event and automatically recycle power and reboot the device. An additional heavy-ion test was scheduled to validate the operation of the recovery circuitry and the continuing functionality of the ADV212 after a substantial number of latch-up events. As a secondary goal, more precise data would be gathered by an improved test method, described in this test report.

single event latch-ups (SEL)↗