Rad-Hard Beyond CMOS Reservoir Computing with Continual Learning [Poster]
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Wells, William [Savannah River National Laboratory↗
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High-performance low-power CMOS memories using silicon-on-sapphire technology.
MOS/silicon-on-sapphire (SOS) technology is shown to permit the realization of large-scale integrated arrays that combine the best features of monolithic bipolar and MOS technologies. The perfect isolation and reduced capacitance of SOS technology make possible static MOS circuits with nearly an order-of-magnitude improvement in speed and dynamic power dissipation over their monolithic counterparts. CMOS/SOS memory arrays have been fabricated with speeds comparable to TTL bipolar memory arrays even when operated at TTL compatible levels. Quiescent power dissipation of two described arrays is typically less than 1 microwatt/bit. The SOS/MOS technology is compatible with both aluminum and self-aligned silicon-gate processing.
Boleky, E. J.↗
CMOS array design automation techniques
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.
Ramondetta, P.↗
Prediction and measurement results of radiation damage to CMOS devices on board spacecraft
All the currently available results of the flight experiment for all the individually instrumented 130 transistors, relating to both biased and unbiased n- and p-channel RCA and -channel AMI devices were presented. The predictions of dose levels based on a detailed analysis of the space radiation environment as encountered by Explorer-55 and calculated by one dimensional slab geometry, and three dimensional spherical geometry were cited.
Stassinopoulos, E. G.↗
Optical scanning tests of complex CMOS microcircuits
The new test method was based on the use of a raster-scanned optical stimulus in combination with special electrical test procedures. The raster-scanned optical stimulus was provided by an optical spot scanner, an instrument that combines a scanning optical microscope with electronic instrumentation to process and display the electric photoresponse signal induced in a device that is being tested.
Levy, M. E.↗
Electrical characterization of standard and radiation-hardened RCA CDP1856D 4-BIT, CMOS, bus buffer/separator
Tests performed to determine accuracy and efficiency of bus separators used in microprocessors are presented. Functional, AC parametric, and DC parametric tests were performed in a Tektronix S-3260 automated test system. All the devices passed the functional tests and yielded nominal values in the parametric test.
Stokes, R. L.↗
Electrical Characterization of Hughes HCMP 1853D and RCA CDP1853D N-bit, CMOS, 1-of-8 Decoder Microcircuits
Electrical characterization tests were performed on two different manufactured types of integrated circuits. The devices were subjected to functional and AC and DC parametric tests at ambient temperatures of -55 C, -20 C, 25 C, 85 C, and 125 C. The data were analyzed and tabulated to show the effect of operating conditions on performance and to indicate parameter deviations among devices in each group. Accuracy was given precedence over test time efficiency where practical, and tests were designed to measure worst case performance.
Stokes, R. L.↗
Expansion of CMOS array design techniques
The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.
Feller, A.↗
Activation energies of thermal annealing of radiation-induced damage in n- and p-channels of CMOS integrated circuits
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Danchenko, V.↗
Activation energies of thermal annealing of radiation-induced damage in n- and p-channels of CMOS integrated circuits. II
The procedures described by Danchenko et al. (1980) are applied to devices of RCA's Z-process (100,000 rad-hard). A thermal annealing investigation of the Z-process reveals an annealing behavior of the p-channels that is anomalous when compared with the p-channels of the commercial and J-processes. It is noted that the thermal annealing-induced shift of the threshold potential extends far below the original value; this necessitated the development of a new mathematical treatment, the treatment presented in the paper.
Danchenko, V.↗
A radiation hardened 256 x 4 bulk CMOS RAM
A radiation hardened version of the C2L process has been developed that utilizes all-low-temperature processes subsequent to channel oxidation. This process has been used on 1K RAMS. The RAMs functioned reliably at a dose of 200,000 rads (Si) and failed at a dose of 500,000 rads (Si). The 1K RAM is capable of operating from 7.5 to 12 volts and has an access time from address change of 160 nsec at 10 volts
Napoli, L. S.↗
Thermal annealing of radiation damage in CMOS ICs in the temperature range -140 C to +375 C
Annealing of radiation damage was investigated in the commercial, Z- and J-processes of the RCA CD4007A ICs in the temperature range from -140 C to +375 C. Tempering curves were analyzed for activation energies of thermal annealing, following irradiation at -140 C. It was found that at -140 C, the radiation-induced shifts in the threshold potentials were similar for all three processes. The radiation hardness of the Z- and J-process is primarily due to rapid annealing of radiation damage at room temperature. In the region -140 to 20 C, no dopant-dependent charge trapping is seen, similar to that observed at higher temperatures. In the unbiased Z-process n-channels, after 1 MeV electron irradiation, considerable negative charge remains in the gate oxide.
Danchenko, V.↗
CMOS Clock Synchronizer
Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.
Kepp, R. B.↗
An analytical method for predicting CMOS SRAM upsets with application to asymmetrical memory cells
An analytical method was developed to predict the heavy-ion-induced upset rate of static random access memory (SRAM) cells. The method was applied to the design of a memory with asymmetrical cells where the goal was to increase the upset rate in order to increase the number of observed upsets in a space environment. The asymmetry is achieved by increasing the drain area of selected transistors in the cell. Results from the analytical model for a space environment indicate the upset rate for the experimental asymmetrical cell (17.2 upsets/1 kbit-year) will be 4.7 times larger than the upset rate for the minimum-geometry balanced cell (3.6 upsets/1 kbit-year). The asymmetrical SRAM was designed into a test chip intended for the Combined Release and Radiation Effects Satellite (CRRES).
Buehler, Martin G.↗
Thin Rechargeable Batteries for CMOS SRAM Memory Protection
New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.
Crouse, Dennis N.↗
A programmable architecture for CMOS sequential circuits
This paper presents a programmable architecture for sequential pass transistor circuits. The resulting circuits are such that a state machine with N states and M output is constructed using a single layout replicated N + M times.
Whitaker, S.↗
A tunable CMOS constant current source
A constant current source has been designed which makes use of on chip electrically erasable memory to adjust the magnitude and temperature coefficient of the output current. The current source includes a voltage reference based on the difference between enhancement and depletion transistor threshold voltages. Accuracy is +/- 3% over the full range of power supply, process variations, and temperature using eight bits for tuning.
Thelen, D.↗
Ultra low power CMOS technology
This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.
Burr, J.↗