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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

Stirling Convertor Controller Development at NASA Glenn Research Center

For nearly two decades, NASA Glenn Research Center has been supporting the development of radioisotope power systems (RPS). NASA desires higher conversion efficiency RPS options that are reliable and robust with long-life design. Dynamic conversion, such as Stirling and Brayton, offer the potential for higher conversion efficiencies than current RPS but have yet to be demonstrated in a flight application. The RPS program sent out a solicitation to investigate options for dynamic conversion technologies. As a result of this solicitation, four dynamic power convertor (DPC) technologies were selected for design and three are proceeding to the fabrication phase of prototype dynamic convertors. One lesson learned from the Advanced Stirling Radioisotope Generator (ASRG) project is that controller development should be coordinated with the development of a dynamic convertor. As a result of this, Glenn has been utilizing hardware from past Stirling convertor projects, including that of the ASRG, to support controller development for the DPCs. Glenn has developed a strong knowledge base on both analog and digital Stirling DPC controllers and will continue to expand and apply that knowledge to the DPCs. Over the past 15 years, controllers were developed at Glenn, at Lockheed Martin (LM), and by the Johns Hopkins University Applied Physics Laboratory (APL). Various generations of the controllers have been developed as lessons were learned through various component- and system-level tests. Some of the tests performed were fault tolerance, flight acceptance vibration, electromagnetic interference (EMI), spacecraft integration, and extended operation. The fault tolerance test characterized the controller’s ability to handle various fault conditions, including high or low bus power consumption, total open load or short circuit, and replacing a failed controller card while the backup maintains control of the Stirling convertor. The vibration test confirms the controller’s ability to control an Advanced Stirling Convertor (ASC) during launch. The EMI test characterized the alternating-current (AC) and direct-current (DC) magnetic and electric fields emitted by the single ASC and if the controller has an impact on the radiated EMI. Spacecraft integration testing in the Radioisotope Power Systems (RPS), System Integration Laboratory (RSIL) provided insight into the electrical interactions between the representative RPS, its associated control schemes, and realistic electric system loads. The extended operation test allows data to be collected over a period of thousands of hours to obtain long-term performance data of the system. This paper describes the history of controller development at Glenn, tests performed on these controllers, and lessons learned.

Dugala, Gina M.↗
NASA NTRS1973

Glass encapsulation provides extra protection for IC semiconductor devices

Oxide-passivated semiconductor chip is given protective glass coating by means of vapor deposition over metallic substrate of integrated circuit (IC). Method provides more reliable oxide-passivation and hermetic sealing in current use. Chips and scratches incurred during dicing, testing, and assembly are markedly reduced.

Doelp, W. L., Jr.↗
NASA NTRS1985

A dual frequency microstrip antenna for Ka band

For fixed satellite communication systems at Ka band with downlink at 17.7 to 20.2 GHz and uplink at 27.5 to 30.0 GHz, the focused optics and the unfocused optics configurations with monolithic phased array feeds have often been used to provide multiple fixed and multiple scanning spot beam coverages. It appears that a dual frequency microstrip antenna capable of transmitting and receiving simultaneously is highly desirable as an array feed element. This paper describes some early efforts on the development and experimental testing of a dual frequency annular microstrip antenna. The antenna has potential application for use in conjunction with a monolithic microwave integrated circuit device as an active radiating element in a phased array of phased array feeds. The antenna is designed to resonate at TM sub 12 and TM sub 13 modes and tuned with a circumferential microstrip ring to vary the frequency ratio. Radiation characteristics at both the high and low frequencies are examined. Experimental results including radiating patterns and swept frequency measurements are presented.

Lee, R. Q.↗
NASA NTRS1987

In-circuit fault injector user's guide

A fault injector system, called an in-circuit injector, was designed and developed to facilitate fault injection experiments performed at NASA-Langley's Avionics Integration Research Lab (AIRLAB). The in-circuit fault injector (ICFI) allows fault injections to be performed on electronic systems without special test features, e.g., sockets. The system supports stuck-at-zero, stuck-at-one, and transient fault models. The ICFI system is interfaced to a VAX-11/750 minicomputer. An interface program has been developed in the VAX. The computer code required to access the interface program is presented. Also presented is the connection procedure to be followed to connect the ICFI system to a circuit under test and the ICFI front panel controls which allow manual control of fault injections.

Padilla, Peter A.↗
NASA NTRS1991

Monolithic integrated circuit charge amplifier and comparator for MAMA readout

Prototype ICs for the Solar Heliospheric Observatory's Multi-Anode Microchannel Array (MAMA) have been developed; these ICs' charge-amplifier and comparator components were then tested with a view to pulse response and noise performance. All model performance predictions have been exceeded. Electrostatic discharge protection has been included on all IC connections; device operation over temperature has been consistent with model predictions.

Cole, Edward H.↗
NASA NTRS2024

EdgeCortix SAKURA-I Machine-Learning, PCIe Accelerator SEE Heavy Ion Test Report

To enable autonomy in space, machine-learning and computer vision applications become invaluable for sensor processing. However, these algorithms are computationally complex and unfeasible for many embedded central processing units (CPUs) and usually require external coprocessors, such as graphics processing units (GPUs) or accelerators specific to the application, including application specific integrated circuits (ASICs). In power-constrained systems, GPUs tend to consume more power than is acceptable (>40W), so lower-power accelerators have shown promise to provide the performance needed under spacecraft constraints. For radiation engineers, developing methodologies that can properly test CPUs, GPUs, and accelerators, and enable comparisons between them remains a necessary complication to solve as the devices become more complex. The methodology in this test aims to be a start in developing a baseline single-event effect (SEE) test for client-device machine learning accelerators. This category of devices do not host their own operating system. This testing campaign is a continuation of a previous 200 MeV proton test performed in January 2024. This report covers two heavy ion tests of the SAKURA-I card: one in April 2024, and one in June 2024. Additional data was needed after the April test due to ion-range issues experienced at higher linear-energy transfers (LETs). These range issues are described in more detail in Section 8. This experiment characterizes SEEs and data error susceptibility of the EdgeCortix SAKURA-I machine-learning accelerator under heavy ions. The device was monitored for single event upsets (SEUs) and single event functional interrupts (SEFIs) at the Lawrence Berkeley National Laboratory’s 88-inch cyclotron. The SAKURA-I board accelerates machine-learning inference applications on a host computer through a PCIex16 connection. For the purposes of devising an end to end automated analysis workflow for this experiment, the YOLO-V5 and SSD300 objection-detection models, and the ResNet-50, EfficientNet, and MobileNetV2 image classification models were used as a representative suite of analytical machine-learning models.

Seth S Roffe↗
NASA NTRS1992

Autonomous power system brassboard

The Autonomous Power System (APS) brassboard is a 20 kHz power distribution system which has been developed at NASA Lewis Research Center, Cleveland, Ohio. The brassboard exists to provide a realistic hardware platform capable of testing artificially intelligent (AI) software. The brassboard's power circuit topology is based upon a Power Distribution Control Unit (PDCU), which is a subset of an advanced development 20 kHz electrical power system (EPS) testbed, originally designed for Space Station Freedom (SSF). The APS program is designed to demonstrate the application of intelligent software as a fault detection, isolation, and recovery methodology for space power systems. This report discusses both the hardware and software elements used to construct the present configuration of the brassboard. The brassboard power components are described. These include the solid-state switches (herein referred to as switchgear), transformers, sources, and loads. Closely linked to this power portion of the brassboard is the first level of embedded control. Hardware used to implement this control and its associated software is discussed. An Ada software program, developed by Lewis Research Center's Space Station Freedom Directorate for their 20 kHz testbed, is used to control the brassboard's switchgear, as well as monitor key brassboard parameters through sensors located within these switches. The Ada code is downloaded from a PC/AT, and is resident within the 8086 microprocessor-based embedded controllers. The PC/AT is also used for smart terminal emulation, capable of controlling the switchgear as well as displaying data from them. Intelligent control is provided through use of a T1 Explorer and the Autonomous Power Expert (APEX) LISP software. Real-time load scheduling is implemented through use of a 'C' program-based scheduling engine. The methods of communication between these computers and the brassboard are explored. In order to evaluate the features of both the brassboard hardware and intelligent controlling software, fault circuits have been developed and integrated as part of the brassboard. A description of these fault circuits and their function is included. The brassboard has become an extremely useful test facility, promoting artificial intelligence (AI) applications for power distribution systems. However, there are elements of the brassboard which could be enhanced, thus improving system performance. Modifications and enhancements to improve the brassboard's operation are discussed.

Merolla, Anthony↗
NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗
NASA NTRS2001

A Comparison of Three-Dimensional Simulations of Traveling-Wave Tube Cold-Test Characteristics Using CST MICROWAVE STUDIO and MAFIA

Previously, it was shown that MAFIA (solutions of Maxwell's equations by the Finite Integration Algorithm), a three-dimensional simulation code, can be used to produce accurate cold-test characteristics including frequency-phase dispersion, interaction impedance, and attenuation for traveling-wave tube (TWT) slow-wave structures. In an effort to improve user-friendliness and simulation time, a model was developed to compute the cold-test parameters using the electromagnetic field simulation software package CST MICROWAVE STUDIO (MWS). Cold-test parameters were calculated for several slow-wave circuits including a ferruled coupled-cavity, a folded waveguide, and a novel finned-ladder circuit using both MWS and MAFIA. Comparisons indicate that MWS provides more accurate cold-test data with significantly reduced simulation times. Both MAFIA and MWS are based on the finite integration (FI) method; however, MWS has several advantages over MAFIA. First, it has a Windows based interface for PC operation, making it very user-friendly, whereas MAFIA is UNIX based. MWS uses a new Perfect Boundary Approximation (PBA), which increases the accuracy of the simulations by avoiding stair step approximations associated with MAFIA's representation of structures. Finally, MWS includes a Visual Basic for Applications (VBA) compatible macro language that enables the simulation process to be automated and allows for the optimization of user-defined goal functions, such as interaction impedance.

Chevalier, C. T.↗
NASA NTRS1978

Automated tester for MOS devices

Automated system rapidly diagnoses MOS integrated circuits. Its programed electronics investigate transistor and cell characteristics to compile data needed for screening. Program can be changed rapidly to alter test procedures, test duration, and precision.

Cockrum, R. H.↗
NASA NTRS1984

Status Panel For Video Cassette Recorders

Central array of light-emitting diodes displays status of 30 video cassette recorders (VCR's) monitoring integrated testing of Space Shuttle. Remote status panel linked to VCR's by one 37-conductor cable. Transistor/ transistor logic chips in interface circuit allow LED array to function without drawing power from VCR control circuits.

Talley, G. L., Jr.↗
NASA NTRS1995

Operational characteristics of a 200 C LC parallel resonant circuit

Research efforts are currently underway at the NASA Lewis Research Center to design and demonstrate an inverter capable of operating with a baseplate temperature of 200 C. In support of this project, various electrical components including capacitors, inductors, transformers, cables, and semiconductor switches are being developed or evaluated for integration into the inverter. In this work, a parallel LC resonant circuit was constructed and evaluated under simultaneous electrical and thermal stressing. The tests were performed in the temperature range of 25 to 200 C with an applied voltage of up to 90 V, 20 kHz. The individual components were comprised of high temperature film capacitors and powder core inductors developed in-house. The circuit was characterized in terms of the component currents and case temperatures as well as frequency of resonance as a function of applied bias and temperature. The results obtained, which have indicated good functional stability up to 200 C, are presented and discussed.

Baumann, Eric D.↗
NASA NTRS1973

The NASA computer aided design and test system

A family of computer programs facilitating the design, layout, evaluation, and testing of digital electronic circuitry is described. CADAT (computer aided design and test system) is intended for use by NASA and its contractors and is aimed predominantly at providing cost effective microelectronic subsystems based on custom designed metal oxide semiconductor (MOS) large scale integrated circuits (LSIC's). CADAT software can be easily adopted by installations with a wide variety of computer hardware configurations. Its structure permits ease of update to more powerful component programs and to newly emerging LSIC technologies. The components of the CADAT system are described stressing the interaction of programs rather than detail of coding or algorithms. The CADAT system provides computer aids to derive and document the design intent, includes powerful automatic layout software, permits detailed geometry checks and performance simulation based on mask data, and furnishes test pattern sequences for hardware testing.

Gould, J. M.↗
NASA NTRS1978

Elevation scanning laser/multi-sensor hazard detection system controller and mirror/mast speed control components

The electro-mechanical and electronic systems involved with pointing a laser beam from a roving vehicle along a desired vector are described. A rotating 8 sided mirror, driven by a phase-locked dc motor servo system, and monitored by a precision optical shaft encoder is used. This upper assembly is then rotated about an orthogonal axis to allow scanning into all 360 deg around the vehicle. This axis is also driven by a phase locked dc motor servo-system, and monitored with an optical shaft encoder. The electronics are realized in standard TTL integrated circuits with UV-erasable proms used to store desired coordinates of laser fire. Related topics such as the interface to the existing test vehicle are discussed.

Craig, J.↗
NASA NTRS1987

Tester for Multiple-Conductor Cables

Portable testing circuit enables technician to determine quickly wiring errors in multiple-conductor electrical cable or terminal connectors. Active unit tester made of inexpensive integrated circuits and other readily available components. Timer and one-shot generate pulses counted by shift registers. Shift-register output terminals wired to connector pins so voltage applied to each pin in sequence.

Wirth, Manfred N.↗
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
NASA NTRS2008

Disturb testing in flash memories

Non-volatile memory technology as defined by NAND architecture flash memory continues to lead the process scaling and device shrinking efforts of the entire integrated circuit industry. 45- nm technology nodes are now producing commercial 32Gb devices. These latest 32Gb devices are pioneering new charge trapping memory cell technologies using metal gates and high-k dielectric materials. These cells are called TANOS and consist of tantalum-nitride, aluminum oxide (high k material), nitride, oxide, and silicon. Such high-density memories continue to revolutionize commercial electronics in terms of new high-speed data architectures and significant reductions in overall power and weight consumption. In stark contrast, nearly all science-based interplanetary and earth-orbiting NASA spacecraft are still designing in and around mid-1980s-level non-volatile technology with 1Mb Electrically Erasable Read-Only Memory (EEPROM) devices. NASA has typically shunned the use of modern flash devices because of radiation and reliability concerns due to the commercial-offthe– shelf (COTS) nature of the NAND flash technology. Given the significant potential increases in overall system capability these modern flash devices could bring to NASA missions, it is important to continue to investigate these devices. This report will investigate certain portions of the reliability performance of NAND flash devices, specifically the disturb properties. Understanding the possible limitations such new non-volatile memory technology presents to NASA is the goal of this report.

Freie, Michael↗
NASA NTRS2009

Tests of Low-Noise MMIC Amplifier Module at 290 to 340 GHz

A document presents data from tests of a low-noise amplifier module operating in the frequency range from 290 to 340 GHz said to be the highest-frequency low-noise, solid-state amplifier ever developed. The module comprised a three-stage monolithic microwave integrated circuit (MMIC) amplifier integrated with radial probe MMIC/waveguide transitions and contained in a compact waveguide package, all according to the concepts described in the immediately preceding article and in the referenced prior article, "Integrated Radial Probe Transition From MMIC to Waveguide" (NPO-43957), NASA Tech Briefs Vol. 31, No. 5 (May 2007), page 38. The tests included measurements by the Y-factor method, in which noise figures are measured repeatedly with an input noise source alternating between an "on" (hot-load) condition and an "off" (cold-load) condition. (The Y factor is defined as the ratio between the "on" and "off" noise power levels.) The test results showed that, among other things, the module exhibited a minimum noise figure of about 8.7 dB at 325 GHz and that the gain at that frequency under the bias conditions that produced the minimum noise figure was between about 9 and 10 dB.

Gaier, Todd↗