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A two-mode squeezed microresonator-based frequency comb is demonstrated with CMOS-compatible silicon nitride integrated photonic circuits. Seventy quantum modes, in a span of 1.3 THz, are generated in an integrated Kerr microresonator at telecommunication wavelengths.
Quantum frequency conversion serves a key role in the realization of hybrid quantum networks by interfacing between wavelength-incompatible platforms. Here we present what is believed to be the first quantum frequency converter connecting visible and telecom domains on a silicon nitride (SiN) chip, using Bragg-scattering four-wave mixing to upconvert heralded single photons from 1260 to 698 nm, which covers a 192 THz span. We examine the noise sources in SiN and devise approaches to suppress noise photons at the source and target frequencies to enable measurements at the single-photon level. We demonstrate an on-chip conversion efficiency of 5% in photon flux and describe design modifications that can be implemented to significantly improve it. Our results pave the way for the implementation of complementary metal-oxide-semiconductor (CMOS)-compatible devices in quantum networks.
Frequency-bin encoding offers tremendous potential in quantum photonic information processing, in which a single waveguide can support hundreds of lightpaths in a naturally phase-stable fashion. This stability, however, comes at a cost: arbitrary unitary operations can be realized by cascaded electro-optic phase modulators and pulse shapers, but require nontrivial numerical optimization for design and have thus far been limited to discrete tabletop components. In this article, we propose, formalize, and computationally evaluate a new paradigm for universal frequency-bin quantum information processing using acousto-optic scattering processes between distinct transverse modes. We show that controllable phase matching in intermodal processes enables 2 × 2 frequency beamsplitters and transverse-mode-dependent phase shifters, which together comprise cascadable FRequency-transverse-mODe Operations (FRODOs) that can synthesize any unitary via analytical decomposition procedures. Modeling the performance of both random gates and discrete Fourier transforms, we demonstrate the feasibility of high-fidelity quantum operations with existing integrated photonics technology, highlighting prospects of parallelizable operations achieving 100% bandwidth utilization. Our approach is realizable with CMOS technology, opening the door to scalable on-chip quantum information processing in the frequency domain.
Abstract We present an electrically switchable, compact metasurface device based on the metallic polymer PEDOT:PSS in combination with a gel polymer electrolyte. Applying square-wave voltages, we can reversibly switch the PEDOT:PSS from dielectric to metallic. Using this concept, we demonstrate a compact, standalone, and CMOS compatible metadevice. It allows for electrically controlled ON and OFF switching of plasmonic resonances in the 2–3 µm wavelength range, as well as electrically controlled beam switching at angles up to 10°. Furthermore, switching frequencies of up to 10 Hz, with oxidation times as fast as 42 ms and reduction times of 57 ms, are demonstrated. Our work provides the basis towards solid state switchable metasurfaces, ultimately leading to submicrometer-pixel spatial light modulators and hence switchable holographic devices.
The optical and electronic tunability of the conductive polymer poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) has enabled emerging applications as diverse as bioelectronics, flexible electronics, and micro- and nano-photonics. High-resolution spatial patterning of PEDOT:PSS opens up opportunities for novel active devices in a range of fields. However, typical lithographic processes require tedious indirect patterning and dry etch processes, while solution-processing methods such as ink-jet printing have limited spatial resolution. Here, we report a method for direct write nano-patterning of commercially available PEDOT:PSS through electron-beam induced solubility modulation. The written structures are water stable and maintain the conductivity as well as electrochemical and optical properties of PEDOT:PSS, highlighting the broad utility of our method. We demonstrate the potential of our strategy by preparing prototypical nano-wire structures with feature sizes down to 250 nm, an order of magnitude finer than previously reported direct write methods, opening the possibility of writing chip-scale microelectronic and optical devices. We finally use the high-resolution writing capabilities to fabricate electrically-switchable optical diffraction gratings. We show active switching in this archetypal system with >95 % contrast at CMOS-compatible voltages of +2 V and -3 V, offering a route towards highly-miniaturized dynamic optoelectronic devices.
The performance of Nuclear Deterrence (ND) systems could be improved by adopting advanced commercial CMOS technologies. However, the radiation hardness of these ND systems must be assured. This project quantified dose rate upset thresholds, allowing us to evaluate whether advanced commercial technologies can be used in rad hard applications. This project also evaluated the susceptibility of advanced commercial technologies to neutron displacement damage and single event effects, and developed hardness assurance methods. As a result of this work, Sandia is now collaborating more closely with DoD agencies and their contractors to understand and improve the radiation hardness of advanced commercial technologies. Sandia Capabilities (SPHINX, lon Beam Lab, FPGA test capabilities) were developed and are being utilized by other programs. Staff were trained to do radiation survivability testing and developed proposals that were funded. Internal and external collaborations and partnerships were developed, including with Georgia Tech. This project received the Best Paper award at the 2019 Hardened Electronics And Radiation Technology (HEART) Conference.
A recently completed LDRD project has provided a new facility at Sandia for testing effects of energetic neutrons on electronic components. 14 MeV neutrons are produced with a deuterium ion beam onto a thin-film tritide target. The goal of the project was to increase the neutron fluence to levels needed for radiation effects testing and qualification. This goal was achieved through two technical advances. First, a new multi-layer target concept was developed to reduce the rate of tritium loss from the target by isotope exchange, thereby reducing tritium usage and increasing target lifetime. The second advance was the construction of a new test chamber designed to maximize neutron flux at test locations. Together, these increased the available neutron fluence by several orders of magnitude. This new capability is being used in tests for Sandia nuclear weapon programs, evaluation of commercial parts such as highly-scaled CMOS SRAM lCs, and tests of new devices under development at Sandia such as lll-V HBTs, gallium nitride high-voltage diodes, and for fundamental studies of physical mechanisms of device failure.
Spintronics is an approach to energy-efficient electronics beyond silicon CMOS that utilizes the electron’s spin degree of freedom for memory and logic. The record spin diffusion length in graphene has generated considerable interest in two dimensional (2D) materials (i.e. graphene and beyond) as a platform for spintronics. Magnetism in 2D van der Waals materials may offer additional opportunities for tunability via strain, external fields, and layer-dependent quantum effects. The inherently atomic-scale nature of exchange interactions and the inherently all-surface nature of 2D sheets motivate an integrated approach combining atomic-scale magnetic characterization, epitaxial growth, and nanodevice fabrication. The mission of the research is to develop and utilize atomic-scale imaging of spin and magnetism via spin-polarized scanning tunneling microscopy (STM) in conjunction with atom-by-atom materials growth via molecular beam epitaxy (MBE) and nanoscale device fabrication to explore new frontiers of spintronics and quantum science in 2D materials. The PIs are particularly motivated by understanding how the magnetic and spin-dependent properties at the atomic scale lead to interesting and potentially useful phenomena in spintronic devices at the macroscopic scale.
The ability to train deep neural networks on large data sets have made significant impacts onto artificial intelligence, but consume significant amounts of energy due to the need to move information from memory to logic units. In-memory "neuromorphic" computing presents an alternative framework that processes information directly on memory elements. In-memory computing has been limited by the poor performance of the analogue information storage element, often phase-change memory or memristors. To solve this problem, we developed two types of "redox transistors" using TiO 2 (anatase) which stores analogue information states through the electrochemical concentration of dopants in the crystal. The first type of redox transistor uses lithium as the electrochemical dopant ion, and its key advantage is low operating voltage. The second uses oxygen vacancies as the dopant, which is CMOS compatible and can retain state even when scaled to nanosized dimensions. Both devices offer significant advantages in terms of predictable analogue switching over conventional filamentary-based devices, and provide a significant advance in developing materials and devices for neuromorphic computing.
Sandia National Laboratories was asked to provide a technical feasibility assessment on whether programmability is a viable means to address the radiation levels in the Export Administration Regulations (EAR). Most (if not all) modern Complementary Metal Oxide Semiconductor (CMOS) technologies will exceed at least one of the EAR radiation criteria inherently, there is no longer anything “special” about domestic parts or technologies that exceed EAR radiation criteria. A modern part today is not “designed” to exceed EAR criteria and in fact a part would need to be “specially designed” to fail to meet all of these criteria. And although it is possible to design a part to fail to meet the EAR radiation criteria in an unprogrammed state, such a part would be difficult to design in some technologies, may not achieve the ultimate radiation levels desired, would fail to meet core reliability principles, and may be unsuitable for high consequence applications.
Engineers at Sandia National Laboratories (SNL) have used quartz - based clock oscillators in various missions since the 1980s. As such, the design of these frequency control devices requires a high degree of reliability and producibility. The quartz clock oscillators designed at SNL have evolved over many years and are currently developed in house and fabricated using SNLs internal CMOS foundry. They are designed to operate in harsh environments, including temperature, radiation, shock and vibration. This report documents the methodology behind the design of quartz clock oscillators developed at SNL and includes an overview of quartz resonator technology and usage guidelines and a detailed overview of oscillator circuits.
This work evaluated the iX Cameras iSpeed 727, a commercial CMOS-based continuous- recording high-speed camera. Various parameters of importance in the scheme of accurate time-resolved measurements and photonic quantification have been measured under controlled conditions on the bench, using state-of-the-art instrumentation. We will detail the procedures and results of the tests laid out to measure sensor sensitivity, linearity, signal-to-noise ratio and image lag. We also looked into the electronic shutter performance and accuracy, as exposure time is of particular interest to high-speed imaging. The results of the tests show that this camera matches or exceeds the performance of competing units in most aspects, but that, as is the case for other high-speed camera systems, corrections are necessary to make full use of the image data from a quantitative perspective.
Hybrid-CMOS (hCMOS) nanosecond x-ray imagers are a powerful timeresolved HED (high-energy-density) diagnostic due to their sensitivity to visible light, x-rays, and charged particles. However, significant pseudosinusoidal background oscillations have been observed in these sensors when exposed to an early incident excitation, a phenomenon that has been experimentally linked the sensor’s bond wire inductance. We analyze the oscillations both in the time domain and spatially to account for variations on the pixel level. Both theoretical techniques and analysis of experimental data have shown that the oscillations are a global sensor phenomenon. In addition, we effectively describe the oscillations with a physics-based model, giving further insight into the processes affecting them. This technique allows the hCMOS user to subtract out the oscillations from their measurements and improve accuracy.
Large-scale date centers are becoming increasingly limited by the capacity of interconnects due to the rapid increasing power consumption and bandwidth demands driven by the rigorous down scaling of CMOS critical dimensions in according with the Moore’s Law. As a result of the continuing bandwidth scaling, optical interconnects based on parallel optics, where data are simultaneously transmitted along more than one lane, have becoming a preferred interconnected solution over copper cables. To building an efficient optical interconnect system, optical coupling between different elements, such as optical fibers, photonics chips, is a critical step, which is challenging due to the mode mismatch of varies optical ports. In this project, we proposed and demonstrated an optical interfacing scheme, which provided a light coupling approach with low energy loss, broadband operation, high alignment tolerance and compatible with scalable fabrication and testing. Here, the mode transformation is achieved by a total internal reflection from a chip integrated microscale freefrom surface. Due to the enormous light wavefront manipulating ability associated with the gigantic design space, the freeform couplers platform is universally applicable to a wide range of optical coupling scenarios, such as the interfacing between a waveguide to a fiber, another waveguide, surface normal device, or free space.
This project uses a quantum simulation technique to reveal the true conducting properties of novel atomic precision advanced manufacturing materials. With Moore's law approaching the limit of scaling for the CMOS technology, it is crucial to provide the best computing power and resources to National Security missions. Atomic precision advanced manufacturing-based computing systems can become the key to the design, use, and security of modern weapon systems, critical infrastructure, and communications. We will utilize the state-of-the-art computational methodology to create a predictive simulator for p-type atomic precision advanced manufacturing systems, which may also find applications in counterfeit detection and anti-tamper.
The Neutron Imaging team is readying for the NIS2 polar LOS development and future improvements to data quality on all LOS given consistently higher yields at NIF. Next-gen nano guide scintillators for NIS2 and CMOS cameras to replace outdated CCDs will be studied. Digital image plates will be tested for better data quality on passive imaging systems. The transition into the ignition regime is expected to show a significant signature in the ablator areal density. In the marginal ignition regime, a decrease of 12C-rhoR (ablator areal density) is expected but once the burn propagation produces a shock and compresses the ablator the trend reverses. GCD with the PD-PMT can resolve this effect in the ablator areal density by a temporal shift in the carbon signal. To give quantitative results a calibration of the detector for the Hohlraum/TMP signal is needed. Shots using Al, Si, and Au pucks will yield the needed information to move forward with this project.
Neuromorphic systems can be realized by a variety of algorithms and architectures. A common understanding is that spiking neuromorphic designs, which encode information into spatio-temporal spiking events, are both a biologically-accurate and efficient way of processing information. However, representing the information through timing relationships induces sophisticated circuit designs in traditional CMOS-based implementations. In recent years, high-capacity resistive memory (RRAM, aka, memristor) has demonstrated great potential in mimicking synaptic behaviors. Several RRAM-based spiking neuromorphic designs exist, most of which focus on rate coding schemes. These designs simplify circuit implementations of neuron models and explore challenges such as unsatisfactory speed, resolution, and performance. As an alternative, we will explore temporal coding spiking neuromorphic systems that encode information as the relative timing of neuron activations (spikes), which have been proven to be more adaptive and energy-efficient. Developing a neuromorphic system for spiking neural network (SNN) inference and online training, however, faces some major technical challenges: (1) It lacks circuit implementation support for temporal-coding SNN to achieve satisfying power efficiency and accuracy; (2) Although existing research works have investigated memristive synapse and neuron designs for spike-timing-dependent plasticity, the non-ideal conditions in implementation, such as device variations and signal degradation, degrade online learning accuracy of large scale systems; and (3) Non-optimized, inter-layer data traffic in SNNs, leads to unnecessary data communication costs. In this project, we plan to address these challenges by a hardware and software co-design framework that incorporates solutions at the circuit, architecture, and algorithm levels. At the circuit-level, we will elaborate on the in-situ SNN processing element designs for supporting both inference and online training modes. Variation-aware schemes will be studied to improve reliability. At the architecture level, we propose a pipelined, asynchronous architecture to retain the timing resolution of spikes. At the algorithm level, we will investigate an innovative SNN training algorithm for enabling activation sparsification and reducing unnecessary data communication costs. This neuromorphic system will provide an effective solution to real-life energy-constrained applications and significantly contribute to the exploration of next-generation high-performance computing systems under the DOE context.
In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.