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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

High-Temperature Probe Station Developed to Characterize Microwave Devices Through 500 C

A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.

Downey, Alan N.↗
NASA NTRS2008

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

Neudeck, Philip G.↗
NASA NTRSDate not supplied

Processing Choices for Achieving Long Term IC Operation at 500 °C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

silicon carbide↗
NASA NTRS2023

Processing Choices for Achieving Long Term IC Operation at 500° C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

SiC, JFET, Integrated Circuits, High-Temperature, ↗
NASA NTRS2004

Measurement of Thin Film Integrated Passive Devices on SiC through 500 C

Wireless communication in jet engines and high temperature industrial applications requires FD integrated circuits (RFICs) on wide bandgap semiconductors such as Silicon Carbide (SiC). In this paper, thin-film NiCr resistors, MIM capacitors, and spiral inductors are fabricated on a high purity semi-insulating 4H-SiC substrate. The devices are experimentally characterized through 50 GHz at temperatures of up to 500 C and the equivalent circuits are deembedded from the measured data. It is shown that the NiCr resistors are stable within 10% to 300 C while the capacitors have a value stable within 10% through 500 C.

Schwartz, Zachary D.↗
NASA NTRS2006

SiC Field Effect Transistor Technology Demonstrating Prolonged Stable Operation at 500 C

While there have been numerous reports of short-term transistor operation at 500 degree C or above, these devices have previously not demonstrated sufficient long-term operational durability at 500 degree C to be considered viable for most envisioned applications. This paper reports the development of Silicone Carbi field effect transistors capable of long-term electrical operation at 500 degree C. A 6H-SiC MESFET was packaged and subjected to continuous electrical operation while residing in a 500 degree C oven in oxidizing air atmosphere for over 2400 hours. The transistor gain, saturation current (IDSS), and on-resistance (RDS) changed by less than 20% from initial values throughout the duration of the biased 500 degree C test. Another high-temperature packaged 6H-SiC MESFET was employed to form a simple one-stage high-temperature low-frequency voltage amplifier. This single-stage common-source amplifier demonstrated stable continuous electrical operation (negligible changes to gain and operating biases) for over 600 hours while residing in a 500 degree C air ambient oven. In both cases, increased leakage from annealing of the Schottky gate-to-channel diode was the dominant transistor degradation mechanism that limited the duration of 500 degree C electrical operation.

Neudeck, Philip G.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS2023

Metal Contact Processing Experiments Towards Realizing 500 °C Durable RF 4H-SiC BJTs

This paper presents results from metal contact processing experiments towards the implementation of durable 500 °C high-frequency 4H-SiC bipolar junction transistors (BJTs) . Specifically, p -type ohmic contacts have been demonstrated on a 0.25 μm-thick p -type homoepitaxial layer of doping 8 x 10 18 ± 4 x 10 18 cm -3 . Preliminary current-voltage characteristics of fabricated BJTs are presented.

4H-SiC BJT↗
NASA NTRS2000

Thin and Thick Films Materials Based Interconnection Technology for 500 C Operation

Precious metal based thick-film material was used for printed wires, wire bond pads, test lead-attach, and conductive die-attach for high temperature (up to 500 C and beyond) chip level packaging. A SiC Shottky diode with a thin-film coated backside was attached to a ceramic substrate using precious metal based thick-film material as the electrically conductive bonding layer. After a 500-hour soak test in atmospheric oxygen, these basic interconnection elements, including attached test diode survived both electrically and mechanically. The electrical resistance of these interconnections (including thick-film printed wire/pad, bonded wire, and test lead attach) were low and stable at both room and elevated temperatures. The electrical resistance of the die-attach interface estimated by I-V characterization of the attached diode, during and after high temperature heat treatment, remained desirably low over the course of a 500-hour anneal. Further durability testing of this high temperature interconnection technology is also discussed.

Chen, Liang-Yu↗
NASA NTRS1981

Surface tension of natural silicate melts from 1,200-1,500 C and implications for melt structure

The surface tension between silicate liquid and gas is measured for four lava compositions (limburgite to andesite) from 1,200 to 1,500 C. It is noted that the magnitude of surface tension (gamma) is in the range 350-370 dynes/cm. Variations found in gamma as a function of liquid composition are small and have no obvious relation to liquid composition. Gamma is also found to vary little with furnace atmosphere - air, Ar, CO2, H2, CO and their mixtures. It is found that a relaxation time of hours to days, depending on temperature, is required before reproducible results can be obtained from originally crystalline starting material. The reproducible temperature dependence of gamma for complex silicate liquid solution is found to be small, positive, and a relatively simple function of liquid composition.

Walker, D.↗
NASA NTRS2025

System for Long-Duration Electrical Testing of SiC IC Generation 12 Chips at 500 °C

The system described in this report is an improved testing rig designed to enhance measurement flexibility, provide a compact oven footprint, and reduce costs for parallel oven-testing silicon carbide (SiC) integrated circuit devices at 500 °C for long durations (greater than 100 h). The testing rig design was characterized in terms of the ovens’ internal and external temperatures, system noise, and the leakage properties of their substrate/inner boards, where the devices under test (DUTs) reside. The test rig employs a National Instruments (NI) Peripheral Component Interconnect eXtensions for Instrumentation (PXI) measurement system, room-temperature pin-switching/customizing boards, and high-temperature compact ovens.

Stephanie Booth↗
NASA NTRS2019

Room Temperature Radiation Testing of a 500 °C Durable 4H-SiC JFET Integrated Circuit Technology

Total ionizing dose (TID) and single-event effect (SEE) room-temperature radiation test results are presented for developmental prototype 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) that have demonstrated prolonged operation in extremely high-temperature (500 °C) environments. The devices tested demonstrated over 7 Mrad(Si) TID tolerance and no destructive SEE susceptibility.

Lauenstein, Jean-Marie↗
NASA NTRS2012

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗
NASA NTRS2019

Molten Target Sputtering: Non-Conventional Method for High Mobility Si0.15Ge0.85 Growth at 500°C

Since electrons travel over 100 times faster in Silicon-Germanium (SiGe) than in pure Si due to the low effective masses associated with Ge and SiGe-based devices continue to replace Si-based solid-state electronic devices. SiGe thin film on sapphire was successfully grown at 890°C, using a magnetron sputtering system within heteroepitaxial framework. However, SiGe growth at 890oC is a costly and difficult process to produce as a uniform wafer for semiconductor device manufacturing due to thermal soak times, and geometric thermal shadowing from the wafer holder. To leverage the semiconducting capabilities of SiGe, novel processing techniques for SiGe film growth with decreased thermal loading are required. This paper introduces the Molten Target Sputtering (MTS) method that produces high mobility SiGe on sapphire below 500°C. This non-conventional method has the advantage of high kinetic energy, high-energy latency, and high flux density of sputtered atoms by combining benefits of both magnetron sputtering and thermal evaporation. For the MTS method, a 1~2 mm (depth and width) ring-shaped groove was cut between the center magnet and surrounded by electromagnets creating a circular cavity between the copper plate and source target materials that melt the target material. The SiGe grown from the MTS shows continuous morphology and 99.7% single crystal Si0.15Ge0.85 films. The Hall electron mobilities of the Si0.15Ge0.85 are 456 sq. cmV(exp -1)s(exp -1) and 123.9 sq. cmV(exp -1)s(exp -1) at 5.59 x 10(exp 18) cubic cm and 3.5 x 10(exp 20) cubic cm carrier concentration at 22.38°C, respectively. This is approximately 5.5 times higher than that of Si and similar to the Ge value at equivalent carrier concentrations and temperatures.

High mobility SiGe↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗