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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Thermal and Mechanical Design of a High-Voltage Power Electronics Package: Preprint

Thermal and mechanical design aspects of a power electronic package with 5-kV GaN devices are presented. Through finite element analyses, the impact of different cooling configurations and device location on the thermal performance and reliability of the package was investigated. It was found that placing the devices closer to the direct-bond-copper substrate as opposed to a centered approach in the proposed double-sided-cooling configuration resulted in improved heat dissipation. This approach also reduced the total number of attachment layers, thereby likely improving the reliability of the package. Furthermore, simulations revealed that the device location had a negligible impact on the thermomechanical behavior of the attachment layers, as they are more prone to the local coefficient of thermal expansion mismatch.

27 ARPA - Advanced Research Projects Agency-Energy↗
NASA NTRS2001

Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging

Key to the design of spacecraft for exploration of the outer planets will be the development of highly integrated and mass/volume efficient electronic systems. Exploration of the outer planets will require optimized propulsion approaches which mandates mass minimization. If one looks at a mission such as the Europa Lander, a high mass/volume efficiency feeds back directly into lower mass for radiation shielding. Concurrently the long mission lengths will drive the need for fault isolation and fault tolerance. The ability to build distributed electronic systems is an inherent requirement and one which is enabled by heterogeneous integration. The electronic packaging approach must be capable of interconnecting various components at a scale comparable with that on the components themselves (chip scale) and it must facilitate efficient integration of the electronics with elements of the spacecraft such as structure or antennae. The concept of 'Heterogeneous Integration' is being explored in the System On A Chip (SOAC) Project at JPL. The goal, of this approach to electronic packaging, is to enable the fabrication and assembly of complete electronic subsystems from components fabricated by a range of processes. Included in such a system could be MEMS sensors, SOI mixed signal ASICs, micro scale passive components and micro power. Secondarily the compact size will enable distributed architectures and integrated assemblies. Additional information is contained in the original extended abstract.

DAgostino, S. A.↗
NASA NTRS1995

Japan's electronic packaging technologies

The JTEC panel found Japan to have significant leadership over the United States in the strategic area of electronic packaging. Many technologies and products once considered the 'heart and soul' of U.S. industry have been lost over the past decades to Japan and other Asian countries. The loss of consumer electronics technologies and products is the most notable of these losses, because electronics is the United States' largest employment sector and is critical for growth businesses in consumer products, computers, automobiles, aerospace, and telecommunications. In the past there was a distinction between consumer and industrial product technologies. While Japan concentrated on the consumer market, the United States dominated the industrial sector. No such distinction is anticipated in the future; the consumer-oriented technologies Japan has dominated are expected to characterize both domains. The future of U.S. competitiveness will, therefore, depend on the ability of the United States to rebuild its technological capabilities in the area of portable electronic packaging.

Tummala, Rao R.↗
DOE OSTI2022

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Epoxy underfills can be implemented in electronic packaging to enhance solder joint reliability of surface mounted components. However, it is important for an engineer to have a failure criterion that can be used for failure predictions and redesign of electronic assemblies. For this study, data from epoxy bond failure in mock electronic part assemblies were correlated to finite element analyses to predict adhesive failure initiation. Experiments were performed to determine failure loads for various loading locations and nonlinear viscoelastic analyses were performed for the same loading locations to determine a maximum principal strain failure parameter. Predictions showed that a maximum principal strain failure parameter defined from one test could be used as an indicator of adhesive failure of an epoxy bond undergoing other modes of loading. Failure initiation predictions matched experimental data using a maximum principal strain failure parameter for an epoxy bond undergoing mixed modes of loading for both unfilled and alumina oxide filled 828DEA epoxy. Such experimental setup is deemed appropriate for future epoxy testing.

42 ENGINEERING↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging—Power Die, Power Module, and Converter Level: Part 2

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. Here, to increase power density, performance, efficiency, and reliability-as well as to reduce cost-innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental R&D related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics, packaging materials, thermal materials and interfaces, fluid-based thermal management technologies, reliability, condition monitoring, and prognostics. Latest developments in this area are published as a Special Section on Multiphysics Aspects of Power Electronics Packaging. The first part was published in the May 2024 issue of the IEEE Transactions on Components, Packaging and Manufacturing Technology (Volume 14, Issue 5). The second part of that Special Section is being published in this issue. A brief summary of the papers included in the second part are given below.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Thermal and Mechanical Design of a High-Voltage Power Electronics Package

This paper presents the thermal and mechanical design aspects of a power electronics package with 5-kV GaN devices. Through finite element analyses, we investigated the impact of different cooling configurations and device locations on the thermal performance and reliability of the package. We found that placing the devices closer to the direct bond copper substrate as opposed to a centered approach in the proposed double-sided cooling configuration resulted in improved heat dissipation. This approach also reduced the total number of attachment layers, thereby likely improving the reliability of the package. Furthermore, simulations revealed that the device location had a negligible impact on the thermomechanical behavior of the attachment layers, as they are more prone to the local coefficient of thermal expansion mismatch.

electronic packaging↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging - Power Die, Power Module, and Converter Level - Part 1

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. To increase power density, performance, efficiency, and reliability and reduce cost, innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental research and development related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics; packaging materials; thermal materials and interfaces; fluid-based thermal management technologies; reliability; condition monitoring; and prognostics. To address these important aspects, this Special Section on Multiphysics Aspects of Power Electronics Packaging includes several articles to be published in two parts. More details are given below on the articles included in the first part.

condition monitoring↗
NASA NTRS1996

Probabilistic Fatigue Life Analysis of High Density Electronics Packaging

The fatigue of thin film metal interconnections in high density electronics packaging subjected to thermal cycling has been evaluated using a probabilistic fracture mechanics methodology. This probabilistic methodology includes characterization of thin film stress using an experimentally calibrated finite element model and simulation of flaw growth in the thin films using a stochastic crack growth model.

thermal cycling fatigue of thin film metal interco↗
NASA NTRS2003

Development of reliable electronic packaging solutions for spacecraft avionics miniaturization using embedded passice devices

Miniaturization of electronic packages will play a key rule in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing.

Schatzel, Don↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

electronic packaging↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

High temperature↗