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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

K-band FET amplifier for satellite downlink

State-of-the-art performance is demonstrated with solid-state amplifiers in K-band. The amplifier provides 8.2 watts of power with 39 dB gain over a frequency band of 1.4 GHz. Nonlinearity analyses of solid-state amplifiers suggest that system performance can be improved significantly by using an FET amplifier. Preliminary investigations reveal that the solid-state amplifiers can be space-qualified and can be expected to replace the TWTA in many communication links in the near future. It is pointed out that with improvements in device technology, the power, bandwidth and efficiency of solid-state amplifiers using FETs can be further improved. With FETs operating at a junction temperature of less than 125 C, solid-state amplifiers are inherently reliable, indicating a ten-year mean time to failure.

Goel, J.↗
NASA NTRS1990

An electronically tuned, stable 8415 MHz dielectric resonator FET oscillator for space applications

A voltage-controlled 8415-MHz FET oscillator stabilized by a dielectric resonator is described. The oscillator provides over 3.2-MHz linear electronic tuning range with a flat power output equal to +1.8 dBm (27 C, nominal), a single-sideband noise-to-carrier ratio of -68 dBc/Hz at 1 kHz off carrier, and a frequency-temperature coefficient of 0.54 parts per million/C over a -24 C to 75 C range. The oscillator withstood 150 Krads (Si) of gamma radiation with no significant performance degradation. The overall performance of the FET oscillator is far superior in many ways to that of an equivalent bipolar oscillator for space applications. For space applications, the FET dielectric resonator oscillator (DRO) is preferred over bipolar DRO because of its lower DC power consumption, better thermal frequency stability, linear electronic tunability, and higher RF output power capability.

Mysoor, Narayan R.↗
NASA NTRS1999

Analysis of Carbon Nanotube Field-Effect-Transistors (FETs)

This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.

Yamada, Toshishige↗
NASA NTRS1995

Multi-Shielded p-FET Dosimeter

A compact device was developed for dose measurements where each of four p-FETs has a different shield. Radiation data from the STRV-1b shows that p-FETs can be used to map the radiation inside a spacecraft.

p-FET dosimeters↗
DOE OSTI2026

Multi-Objective Boundary Analysis of Discrete and Integrated SiC FET Modular Non-inverting Buck and Boost Converters for Fuel Cell EVs

This paper presents a multi-objective analysis of discrete and integrated SiC FET-based non-inverting buck-boost converter modules for modular fuel cell electric vehicle (EV) systems. Two converter ratings, 60 kW and 90 kW, are evaluated for both implementations, scalable up to 420 kW and 450 kW, respectively. Performance is assessed across efficiency, volumetric and gravimetric power density, cost, thermal stress, and estimated lifetime, where lifetime is derived from SiC FET B10 power-cycling data and junction temperature variations at rated power. A normalized overall performance index combined with a Pareto-boundary framework is used to identify configurations that optimally balance competing objectives. Results show that most configurations lie on the Pareto front, providing balanced trade-offs, while certain high-power discrete (90 kW at 450 kW) and integrated (60 kW at 180−420 kW) configurations are dominated. In general, discrete modules are more favorable for lower-power modular systems due to higher power density and lower cost, whereas integrated modules become more advantageous at higher power levels due to improved thermal behavior and longer lifetime. These findings provide practical design guidance for scalable fuel cell converter architectures and highlight the importance of system-level trade-offs in modular power electronics design.

Asa, Erdem [ORNL] (ORCID:0000000190884812)↗
DOE OSTI2026

Temperature-Dependent Transport Characteristics of 2D MoS2 Channel FETs Grown Using Salt-Based Precursors

D Transition Metal Dichalcogenides (TMDs), particularly MoS2, are promising candidates for sub-10 nm Gate All Around (GAA) CMOS FETs. Salt-assisted Chemical Vapor Deposition (CVD) enable lateral MoS2 growth at atmospheric pressure and low temperatures. This work analyzes salt-based precursor-driven CVD-grown MoS2 FETs at various temperatures. MoS2 was grown using Ammonium Molybdate salt, sulfurized at 750∘C, and transferred onto p−Si3/SiO2 substrates. At room temperature, threshold voltage (VT) ranged from -35 V to -25 V, with a peak drain current of 1.2μA/μm. As temperature increased above 325K, VT shifted exponentially, and carrier mobility dropped significantly. At 400 K, the gate lost channel control, though gate leakage current remained low. These results are compared with non-salt-based MoS2 growth to assess salt precursor effects.Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (https://www.energy.gov/doe-public-access-plan).

Jones, Andrew [ORNL] (ORCID:0009000233849687)↗
NASA NTRS1966

FET comparator detects analog signal levels without loading analog device

FET comparator circuit detects discrete analog computer output levels without excessively loading the output amplifier of the computer. An FET common source amplifier is coupled by a differential amplifier to a bistable transistor flip-flop. This circuit provides a digital output for analog voltages above or below a predetermined level.

Wallace, H. L.↗
NASA NTRS1986

The 20 GHz power GaAs FET development

The development of power Field Effect Transistors (FET) operating in the 20 GHz frequency band is described. The major efforts include GaAs FET device development (both 1 W and 2 W devices), and the development of an amplifier module using these devices.

Crandell, M.↗
NASA NTRS1988

A 2.3-GHz low-noise cryo-FET amplifier

A cryogenic cooled, low-noise Field Effect Transistor (FET) amplifier assembly for use at 2.2 to 2.3 GHz was developed for the DSN to meet the requirements of a Very Long Baseline Interferometry (VLBI) upgrade. An amplifier assembly was developed at JPL that uses a commercial closed-cycle helium refrigerator (CCR) to cool a FET amplifier to an operating temperature of 15 K. A cooled probe waveguide-to-coaxial transition similar to that used in the research and development Ultra-Low-Noise S-band Traveling Wave Maser (TWM) is used to minimize input line losses. Typical performance includes an input flange equivalent noise contribution of 14.5 K, a gain slope of less than 0.05 dB/MHz across a bandwidth of 2.2 to 2.3 GHz, an input VSWR of 1.5:1 at 2.25 GHz, and an insertion gain of 45 + or - 1 dB across the bandwidth of 2.2 to 2.3 GHz. Three 2.3 GHz FET/CCR assemblies were delivered to the DSN in the spring of 1987.

Loreman, J.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS1992

Evaluation of GaAs FETs for cryogenic readout

Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.

Kirschman, Randall K.↗
NASA NTRS1991

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Eldin, A. G.↗
NASA NTRS2001

The HP 85192B EEFet3 GaAs FET Nonlinear Model Used in the High Efficiency Microwave Power Amplifier (HEMPA)

Most nonlinear circuit analysis programs that exist today were designed primarily for transient analysis. By incorporating more accurate models in simulation programs, accurate predictions of GaAs field effect transistors (FET) behavior can be accomplished. However, should the designer need to simulate GaAs FETs that operate at high DC-to-RF conversion efficiencies, a more sophisticated model is needed. A relevant and appropriate method is called harmonic-balance, as described by Quere et al.

Sims, William Herbert, III↗
NASA NTRS2008

Dual-Input AND Gate From Single-Channel Thin-Film FET

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Miranda, F. A.↗
NASA NTRS2011

Operation of a New Half-Bridge Gate Driver for Enhancement - Mode GaN FETs, Type LM5113, Over a Wide Temperature Range

A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.

Patterson, Richard↗