Optimizing Large-Scale Plasma Simulations on Persistent Memory-based Heterogeneous Memory with Effective Data Placement Across Memory Hierarchy
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Heterogeneous Accelerators of the Memory by the Memory and for the Memory.
Abstract not provided.
Rodrigues, Arun F.↗
JACC.shared: Leveraging HPC Metaprogramming and Performance Portability for Computations That Use Shared Memory GPUs
In this work, we present JACC.shared, a new feature of Julia for ACCelerators (JACC), which is the performanceportable and metaprogramming model of the just-in-time and LLVM-based Julia language. This new feature allows JACC applications to leverage the high-performance computing (HPC) capabilities of high-bandwidth, on-chip GPU memory. Historically, exploiting high-bandwidth, shared-memory GPUs has not been a priority for high-level programming solutions. JACC.shared covers that gap for the first time, thereby providing a highlevel, portable, and easy-to-use solution for programmers to exploit this memory and supporting all current major accelerator architectures. Well-known HPC and AI workloads, such as multi/hyperspectral imaging and AI convolutions, have been used to evaluate JACC.shared on two exascale GPU architectures hosted by some of the most powerful US Department of Energy supercomputers: Perlmutter (NVIDIA A100) and Frontier (AMD MI250X). The performance evaluation reports speedup of up to 3.5× by adding only one line of code to the base codes, thus providing important accelerators in a simple, portable, and transparent way and elevating the programming productivity and performance-portability capabilities for Julia/JACC HPC, AI, and scientific applications.
Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗
Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing
Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.
bio-inspired, energy storage (including batteries ↗
Analysis of memory use for improved design and compile-time allocation of local memory
Trace analysis techniques are used to study memory referencing behavior for the purpose of designing local memories and determining how to allocate them for data and instructions. In an attempt to assess the inherent behavior of the source code, the trace analysis system described here reduced the effects of the compiler and host architecture on the trace by using a technical called flattening. The variables in the trace, their associated single-assignment values, and references are histogrammed on the basis of various parameters describing memory referencing behavior. Bounds are developed specifying the amount of memory space required to store all live values in a particular histogram class. The reduction achieved in main memory traffic by allocating local memory is specified for each class.
Mcniven, Geoffrey D.↗
A general model for memory interference in a multiprocessor system with memory hierarchy
The problem of memory interference in a multiprocessor system with a hierarchy of shared buses and memories is addressed. The behavior of the processors is represented by a sequence of memory requests with each followed by a determined amount of processing time. A statistical queuing network model for determining the extent of memory interference in multiprocessor systems with clusters of memory hierarchies is presented. The performance of the system is measured by the expected number of busy memory clusters. The results of the analytic model are compared with simulation results, and the correlation between them is found to be very high.
Taha, Badie A.↗
Resistive memory for radiation resistant non-volatile memory (NSTRF Final Report)
As space programs increase in number and scope, there is an increasing need for radiation-hardened electronic devices and circuits. In particular, missions to high-radiation environments, such as Europa, would greatly benefit from improved radiation hardness in electronic devices. In pursuit of this goal, resistive memory (RRAM) devices were fabricated at SUNY Polytechnic Institute and evaluated for radiation hardness. Our objectives were to produce RRAM devices resistant to high levels of radiation damage and to demonstrate that these devices would improve mission lifetime in high-radiation environments. Furthermore, the underlying mechanisms of radiation were investigated to provide recommendations for radiation-hardening RRAM devices, which could be applied to any candidate RRAM devices being considered for space applications. Devices were fabricated using several fabrication approaches, including patterning by shadow mask, photolithography-based etching, and photolithography-based liftoff. In each of these cases, total ionizing dose (TID) effects and displacement damage dose (DDD) effects were measured. TID effects from exposure to a 60Co gamma source were not observed to cause changes in device resistance or switching parameters in any experiments, with each device tested to at least 20 Mrad(Si). DDD was measured as radiation-generated oxygen vacancies per cm 3 since oxygen vacancies are generally considered to be the active species involved in switching these devices. The lowest DDD level that caused a device to change resistance state was 10 21 vacancies per cm 3 , and most devices failed at 1022 vacancies per cm 3 . This is an extremely high DDD level, even for RRAM devices, which have been reported to fail in the range of 10 17 -10 20 vacancies per cm 3 . For comparison, an example flash memory device failed at 10 15 vacancies per cm 3 . Vendor-fabricated devices with a similar composition to our own were also tested against TID and DDD. The vendor-fabricated devices did not exhibit changes due to TID, up to the tested level of 30 Mrad(Si). Meanwhile, vendor devices exhibited resistance state changes at 10 21 vacancies per cm 3 , similar to our own devices. These results indicate that Ta0x-based RRAM devices may be particularly resilient to both TID and DDD effects. The very high tolerance to radiation effects is most likely due to the high intrinsic concentration of oxygen vacancies within our devices. Based on X-ray photoelectron spectroscopy (XPS) measurements, there are approximately 10 22 oxygen vacancies per cm 3 in our devices as deposited. Most devices failed when the radiation-induced vacancies reached this level, indicating suggesting that a high intrinsic vacancy concentration protects against lower levels of displacement damage. High vacancy concentration likely also protects against TID by facilitating leakage of trapped charge out of the oxide. The use of a thin switching oxide (25 nm Ta0 x , for our devices) is also expected to improve radiation hardness, as there is less room for charge trapping. Therefore, those wishing to produce very radiation-tolerant RRAM devices can probably achieve this by using a thin oxide that contains a high intrinsic concentration of oxygen vacancies. Our devices appear to be very tolerant of radiation effects, and would greatly increase the expected lifetime of a mission to Europa or another high-radiation target compared to flash memory devices. The similar radiation performance of vendor-fabricated devices is promising for adoption of RRAM devices as radiation-hardened memory devices for use in space. With continued commercial development of these devices, RRAM devices are strong candidates for next-generation memories that are inherently rad-hard.
36 MATERIALS SCIENCE↗
Recoverable distributed shared virtual memory - Memory coherence and storage structures
This paper examines the problem of implementing rollback recovery in multicomputer distributed shared virtual memory environments, in which the shared memory is implemented in software and exists only virtually. A user-transparent checkpointing recovery scheme and new twin-page disk storage management are presented to implement a recoverable distributed shared virtual memory. The checkpointing scheme is integrated with the shared virtual memory management. The twin-page disk approach allows incremental checkpointing without an explicit undo at the time of recovery. A single consistent checkpoint state is maintained on stable disk storage. The recoverable distributed shared virtual memory allows the system to restart computation from a previous checkpoint due to a processor failure without a global restart.
Wu, Kun-Lung↗
Memory object tagged memory monitoring method and system
Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.
Roberts, David A.↗
Intrinsic two-way shape memory effect in a Ni-Mn-Sn metamagnetic shape memory microwire
We report an intrinsic two-way shape memory effect with a fully recoverable strain of 1.0% was achieved in an as-prepared Ni 50 Mn 37.5 Sn 12.5 metamagnetic shape memory microwire fabricated by Taylor-Ulitovsky method. This two-way shape memory effect is mainly owing to the internal stress caused by the retained martensite in austenite matrix, as revealed by transmission electron microscopy observations and high-energy X-ray diffraction experiments. After superelastic training for 30 loading/unloading cycles at room temperature, the amount of retained martensite increased and the recoverable strain of two-way shape memory effect increased significantly to 2.2%. Furthermore, a giant recoverable strain of 11.2% was attained under a bias stress of 300 MPa in the trained microwire. These properties confer this microwire great potential for micro-actuation applications.
36 MATERIALS SCIENCE↗
Measuring color memory in a color glass condensate at electron–ion colliders
The color memory effect is the non-abelian gauge theory analog of the gravitational memory effect, in which the passage of color radiation induces a net relative SU(3) color rotation of a pair of nearby quarks. It is proposed that this effect can be measured in the Regge limit of deeply inelastic scattering at electron–ion colliders.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
GASNet-EX Memory Kinds: Support for Device Memory in PGAS Programming Models
There is an emerging need for adaptive, lightweight communication in irregular HPC applications at exascale, where GPU accelerators provide the majority of available compute cycles. To address this need, Lawrence Berkeley National Lab is developing a programming system to support distributed-memory HPC application development using the Partitioned Global Address Space (PGAS) model. This work includes two major components: UPC++ and GASNet-EX. UPC++ is a C++ template library providing Remote Memory Access (RMA) and Remote Procedure Call (RPC) communication interfaces. GASNet-EX is a portable, high-performance communication middleware library, used by the implementations of UPC++ and many other PGAS programming models. We describe recent advances in GASNet-EX to efficiently implement zero-copy Remote Memory Access (RMA) communication to and from memory on accelerator devices such as GPUs. We demonstrate performance improvements via benchmark results from UPC++ (on Summit) and the Legion programming system (on DGX-1), both using GASNet-EX for communication.
Hargrove, Paul H↗
Method and apparatus for selective and power-aware memory error protection and memory management
A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.
97 MATHEMATICS AND COMPUTING↗
Ion fluxes and memory effects in an Ar–O 2 modulated radiofrequency-driven atmospheric pressure plasma jet
In this work we used molecular beam mass spectrometry to characterize ion fluxes produced by a modulated radiofrequency (RF)-driven atmospheric pressure plasma jet operating in a homogeneous gas environment (Ar + 1% O 2 ). The influence of the RF modulation frequency (100 Hz to 20 kHz) on the ion fluxes was investigated by time-resolved measurements, and the lifetimes of the dominant ions, O 2 + , NO + , O − , O 2 − and O 3 − , were found to be 28 ± 2, 117 ± 8, 7.3 ± 0.4, 17 ± 1 and 23 ± 2 μs, respectively. The absolute ion densities in the near afterglow region were found to be of the order of 1011 cm−3. Significant differences in the dynamics of the positive and negative ions were found; these are explained by the presence of electrons at similar densities in the afterglow produced by electron detachment reactions from negative ions due to the large concentrations of atomic oxygen and singlet delta oxygen. Transitions in ion flux dynamics for different modulation frequencies and at the startup of the plasma were analyzed together with intensified charge coupled device images recording the plasma propagation in order to assess the dynamics of plasma plume propagation and how it is impacted by ‘memory effects’. Quantitative measurements of the ion densities enabling these memory effects are reported. The results in this paper highlight the tremendous impact of memory effects on plasma propagation and the corresponding pre-ionization.
70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
Low-Voltage, CMOS-Free Synaptic Memory Based on Li X TiO 2 Redox Transistors
Neuromorphic computers based on analogue neural networks aim to substantially lower computing power by reducing the need to shuttle data between memory and logic units. Artificial synapses containing nonvolatile analogue conductance states enable direct computation using memory elements; however, most nonvolatile analogue memories require high write voltages and large current densities and are accompanied by nonlinear and unpredictable weight updates. Here, we develop an inorganic redox transistor based on electrochemical lithium-ion insertion into Li X TiO 2 that displays linear weight updates at both low current densities and low write voltages. The write voltage, as low as 200 mV at room temperature, is achieved by minimizing the open-circuit voltage and using a low-voltage diffusive memristor selector. We further show that the Li X TiO 2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade when operating in an electrochemically driven phase transformation regime.
42 ENGINEERING↗
Nanoscale self-healing mechanisms in shape memory ceramics
Abstract Shape memory ceramics, such as yttria-stabilized tetragonal zirconia (YSTZ), offer unique properties including ultra-high operating temperatures and high resistance to oxidation. However, they are susceptible to formation of defects during manufacturing and/or by mechanical deformation. To completely take advantage of their shape memory properties, it is necessary to fully understand the nano-structural evolution of defects under external stimuli. In this study, defect evolution behaviors in YSTZ nanopillars are investigated by atomistic simulations. Two characteristic orientations of $$\left[ {01\bar 1} \right]$$ 01 1 ¯ and [001] are selected to represent the dominant deformation mechanisms of phase transformation and dislocation migration, respectively. Volume expansion associated with the tetragonal to monoclinic phase transformation is observed to promote healing of crack and void. Atom stress analyses reveal stress concentrations along the newly formed monoclinic phase bands. A critical crack width is identified, less than which the crack can be fully closed in compression. For [001]-oriented YSTZ nanopillars, dislocation migration leads to formations of an amorphous phase, which also assist the crack and void closure process. The revealed crack/void healing mechanisms may provide a path for mitigating internal defects that influences the mechanical properties and deformation mechanisms of shape memory ceramics.
Zhang, Ning (ORCID:0000000240661837)↗
Optical memory development. Volume 1: prototype memory system
The design, development, and implementation of a prototype, partially populated, million bit read-write holographic memory system using state-of-the-art components are described. The system employs an argon ion laser, acoustooptic beam deflectors, a holographic beam splitter (hololens), a nematic liquid crystal page composer, a photoconductor-thermoplastic erasable storage medium, a silicon P-I-N photodiode array, with lenses and electronics of both conventional and custom design. Operation of the prototype memory system was successfully demonstrated. Careful attention is given to the analysis from which the design criteria were developed. Specifications for the major components are listed, along with the details of their construction and performance. The primary conclusion resulting from this program is that the basic principles of read-write holographic memory system are well understood and are reducible to practice.
Cosentino, L. S.↗
A ground-based memory state tracker for satellite on-board computer memory
The TOPEX/POSEIDON satellite, currently in Earth orbit, will use radar altimetry to measure sea surface height over 90 percent of the world's ice-free oceans. In combination with a precise determination of the spacecraft orbit, the altimetry data will provide maps of ocean topography, which will be used to calculate the speed and direction of ocean currents worldwide. NASA's Jet Propulsion Laboratory (JPL) has primary responsibility for mission operations for TOPEX/POSEIDON. Software applications have been developed to automate mission operations tasks. This paper describes one of these applications, the Memory State Tracker, which allows the ground analyst to examine and track the contents of satellite on-board computer memory quickly and efficiently, in a human-readable format, without having to receive the data directly from the spacecraft. This process is accomplished by maintaining a groundbased mirror-image of spacecraft On-board Computer memory.
Quan, Alan↗