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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2022

Ruggedness Evaluation of ASTM International Standard Test Methods for Shape Memory Materials: E3097 Standard Test Method for Mechanical Uniaxial Constant Force Thermal Cycling of Shape Memory Alloys

This paper evaluates the ruggedness testing of the newly released ASTM International E3097 Standard Test Method for Mechanical Uniaxial Constant Force Thermal Cycling of Shape Memory Alloys. The ruggedness experiment was designed with eight runs in two replicates, consisting of seven factors of strain rate (ė), heating and cooling rates (Ṫ(heat) and Ṫ(cool), respectively), upper and lower cycle temperatures (UCT and LCT, respectively), hold time (thold), and minimum load (Fmin) imparted on the samples. The results indicate that the hold time factor had no effect on any result variable. The minimum load factor, alternatively, had the greatest effect on several result variables, with the greatest influence on the strains at martensite start and finish (strain variation ~0.1 percent), and the strains at the upper and lower cycle temperatures (strain variation of 0.14 percent). The UCT was found to have a large effect on the austenite and martensite finish tangent line and data intersect, denoted by Af* and Mf*, by ~17 and 4 °C, respectively. The testing methodology, analysis techniques, and resulting conclusions on the ruggedness of the test methods are presented.

shape memory alloy↗
NASA NTRS2023

Ruggedness Evaluation of ASTM International Standard Test Methods for Shape Memory Materials: E3098 Standard Test Method for Mechanical Uniaxial Pre-strain and Thermal Free Recovery of Shape Memory Alloys

This paper evaluates the ruggedness testing of the recently released ASTM International E3098 Standard Test Method for Mechanical Uniaxial Pre-strain and Thermal Free Recovery of Shape Memory Alloys. The ruggedness experiment was designed with eight runs in two replicates, consisting of seven factors: strain rate (ė), heating and cooling rates (Ṫ heat and Ṫ cool , respectively), upper and lower cycle temperatures (UCT and LCT, respectively), hold time (t hold ), and minimum load (F min ) imparted on the samples. The results indicate that the strain rate factor had no effect on any result variable, whereas the minimum load factor had a large effect on several result variables including the austenite start and martensite finish temperatures as well as most of the strain measurements from the thermal cycle. The lower cycle temperature factor had a large effect on the stress at maximum strain during pre-straining (e i ), denoted by S i , at ~7.2 MPa, as well as the A f , at 5.47 °C. Closely following the LCT effect, Ṫ heat was found to have a large effect on the austenite start temperature (A s ), at a value of ~2.72 °C. The testing methodology, analysis techniques, and resulting conclusions on the ruggedness of the test method are presented.

Shape memory alloys↗
NASA NTRS1977

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 1: Development of a high capacity memory element

Several versions of the 100K bit chip, which is configured as a single serial loop, were designed, fabricated and evaluated. Design and process modifications were introduced into each succeeding version to increase device performance and yield. At an intrinsic field rate of 150 KHz the final design operates from -10 C to +60 C with typical bias margins of 12 and 8 percent, respectively, for continuous operation. Asynchronous operation with first bit detection on start-up produces essentially the same margins over the temperature range. Cost projections made from fabrication yield runs on the 100K bit devices indicate that the memory element cost will be less than 10 millicents/bit in volume production.

Besser, P. J.↗
NASA NTRS1984

Measuring Workload Differences Between Short-term Memory and Long-term Memory Scenarios in a Simulated Flight Environment

Four highly experienced Air Force pilots each flew four simulated flight scenarios. Two scenarios required a great deal of aircraft maneuvering. The other two scenarios involved less maneuvering, but required remembering a number of items. All scenarios were designed to be equaly challenging. Pilot's Subjective Ratings for Activity-level, Complexity, Difficulty, Stress, and Workload were higher for the manuevering scenarios than the memory scenarios. At a moderate workload level, keeping the pilots active resulted in better aircraft control. When required to monitor and remember items, aircraft control tended to decrease. Pilots tended to weigh information about the spatial positioning and performance of their aircraft more heavily than other items.

Berg, S. L.↗
NASA NTRS2019

Ruggedness Evaluation of ASTM International Standard Test Methods for Shape Memory Materials: E3097 Standard Test Method for Mechanical Uniaxial Constant Force Thermal Cycling of Shape Memory Alloys

This paper evaluates the ruggedness testing of the newly released ASTM International E3097 Standard Test Method for Mechanical Uniaxial Constant Force Thermal Cycling of Shape Memory Alloys. The ruggedness experiment was designed with eight runs in two replicates, consisting of seven factors of strain rate (ė), heating and cooling rates (T(sub heat) and T(sub cool), respectively), upper and lower cycle temperatures (UCT and LCT, respectively), hold time (t(sub hold)), and minimum load (F(sub min)) imparted on the samples. The results indicate that the hold time factor had no effect on any result variable. The minimum load factor, alternatively, had the greatest effect on several result variables, with the greatest influence on the strains at martensite start and finish (strain variation ~0.1 percent), and the strains at the upper and lower cycle temperatures (strain variation of 0.14 percent). The UCT was found to have a large effect on the austenite and martensite finish tangent line and data intersect, denoted by A(sub f(sup *)) and M(sub f(sup*)), by ~17 and 4 °C, respectively. The testing methodology, analysis techniques, and resulting conclusions on the ruggedness of the test methods are presented.

Benafan, Othmane↗
NASA NTRS2009

On Nibbles and Bytes: The Conundrum of Memory for Space Systems - NASA Electronic Parts and Packaging (NEPP) and Efforts in Memories

Radiation requirements and trends. TID: 1) >90% of NASA applications are < 100 krads-Si in piecepart requirements. a) Many commercial devices (NVM and SDRAMs) meet or come close to this. b) Charge pump TID tolerance has improved an order magnitude over the last 10 years. 2) There are always a few programs with higher level needs and, of course, defense needs SEL: 1) Prefer none or rates that are considered low risk. a) Latent damage is a bear to deal with. 2) As we re packing cells tighter and even with lower Vdd, we re seeing SEL on commercial devices regularly (<90nm). a) Often in power conversion, I/O, or control areas. SEU: 1) It s not the bit errors, it s the SEFIs errors that are the biggest issues. a) Scrubbing concerns for risk, power, speed.

LaBel, Kenneth A.↗
NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
DOE OSTI2026

An Integrated Framework for Memory-Centric Analysis: From Trace Collection to Co-Design

The memory wall phenomenon—where advances in processor performance significantly outpace those in memory subsystems—poses a fundamental challenge for contemporary computing systems. In memory-bound applications, memory subsystem behavior dominates performance, yet existing analysis approaches present significant limitations: detailed microarchitectural simulators require days to weeks to simulate modest workloads; hardware performance counters provide only aggregate statistics that obscure temporal and spatial access patterns; and scaled simulation approaches face challenges in capturing certain behaviors that emerge at larger scales. These limitations reflect a processor-centric design philosophy increasingly misaligned with memory-bound workloads where detailed understanding of memory access patterns, cache hierarchy interactions, and contention is critical for effective optimization. This paper presents an integrated framework for memory-centric analysis that enables effective hardware-software co-design. We describe practical trace collection techniques, including hardware-assisted processor tracing with minimal overhead and portable software-based instrumentation with statistical sampling. We present multi-perspective analysis methods that examine memory behavior from temporal, sequential, spatial, and relational viewpoints, revealing distinct optimization opportunities invisible in aggregate metrics. We detail an architectural modeling framework that uses sampled traces with temporal interpolation and confidence-based filtering to evaluate cache and memory configurations. Evaluation on representative benchmarks demonstrates that this framework achieves practical accuracy (L2 cache errors of 2.64\%, confidence-filtered L3 errors of 9.92\%, bandwidth errors of 7.33\%) while providing substantial speedup (26.8×) over cycle-accurate simulation, enabling rapid design space exploration. We demonstrate how this integrated framework enables systematic identification of both hardware optimizations (memory controller tuning, bank partitioning, NUMA configuration) and software optimizations (data layout restructuring, prefetching strategies, memory-aware scheduling). Through this comprehensive treatment of the memory-centric analysis pipeline—from trace collection through architectural modeling to co-design application—we provide researchers and practitioners with practical techniques for addressing memory bottlenecks in contemporary computing systems.

Gajaria, Dhruv Mayur↗
NASA NTRS2012

Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere with the satellite s primary mission.

MacLeod, Todd↗