Search NASA⌕ Search

SEARCH · Search NASA

Results for “Microelectronics Reliability”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Scaled CMOS Reliability and Considerations for Spacecraft Systems : Bottom-Up and Top-Down Perspectives

The recently launched Mars Science Laboratory (MSL) flagship mission, named Curiosity, is the most complex rover ever built by NASA and is scheduled to touch down on the red planet in August, 2012 in Gale Crater. The rover and its instruments will have to endure the harsh environments of the surface of Mars to fulfill its main science objectives. Such complex systems require reliable microelectronic components coupled with adequate component and system-level design margins. Reliability aspects of these elements of the spacecraft system are presented from bottom- up and top-down perspectives.

derating thermal margin↗
NASA NTRSDate not supplied

NESC Assessment – Recommendations on Use of Commercial-Off-The-Shelf (COTS) Parts for NASA Missions

This is to present the NESC assessment "Recommendations on Use of Commercial-Off-The-Shelf (COTS) Electrical, Electronic, and Electromechanical (EEE) Parts for NASA Missions" at the Microelectronics Reliability and Qualification Workshop hosted by Aerospace Corporation in February 8-10, 2022. The assessment has two Phases, Phase I on NASA Center current practices on use of COTS and Phase II on DoD and FAA current practices on use of COTS and NESC guidance on COTS selection, application and verification processes. Phase I report was published as NASA/TM−20205011579 and NESC-RP-19-01490 in December 2020. The presentation also includes the scope of the Phase II of the assessment, which is expected to be completed in March-April, 2022.

EEE parts↗
NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗
NASA NTRS1967

Temperature-stabilized, triggerable microelectronic astable multivibrator starts reliably

Multiple chip custom block, MIC construction is used to fabricate an ultracompact, low-power astable multivibrator. The design provides a multivibrator that free runs, eliminating lockup, is triggerable, pulling into synchronization with an external signal source, and permits design flexibility for controlling the frequency variations with temperature.

Stebbins, W. J.↗
NASA NTRS1991

Thermal shock testing for assuring reliability of glass-sealed microelectronic packages

Tests were performed to determine if thermal shocking is destructive to glass-to-metal seal microelectronic packages and if thermal shock step stressing can compare package reliabilities. Thermal shocking was shown to be not destructive to highly reliable glass seals. Pin-pull tests used to compare the interfacial pin glass strengths showed no differences between thermal shocked and not-thermal shocked headers. A 'critical stress resistance temperature' was not exhibited by the 14 pin Dual In-line Package (DIP) headers evaluated. Headers manufactured in cryogenic nitrogen based and exothermically generated atmospheres showed differences in as-received leak rates, residual oxide depths and pin glass interfacial strengths; these were caused by the different manufacturing methods, in particular, by the chemically etched pins used by one manufacturer. Both header types passed thermal shock tests to temperature differentials of 646 C. The sensitivity of helium leak rate measurements was improved up to 70 percent by baking headers for two hours at 200 C after thermal shocking.

Thomas, Walter B., III↗