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At least 37 records · Page 2

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NASA NTRS1977

Ionizing radiation effects on SBP9900 microprocessor

The radiation resistance of a 16-bit microprocessor based on integrated injection logic technology has been investigated. Cumulative fluences of 10 to the 12th power to 10 to the 14th power e/sq cm were used in the radiation-resistance study. Complete failure of the microprocessor was noted at a fluence level of 1.2 times 10 to the 14th power e/sq cm. Though the radiation resistance of the microprocessor makes it suited for space applications, reductions in the power dissipation of the device are needed.

Stanley, A. G.↗

NASA NTRS1978

Microprocessor control of a wind turbine generator

A microprocessor based system was used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

Gnecco, A. J.↗

NASA NTRS1978

Microprocessor control of a wind turbine generator

This paper describes a microprocessor based system used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

Gnecco, A. J.↗

NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗

NASA NTRS1980

Distributed microprocessors in a tactical universal modem

The distributed microprocessor system associated with a wideband signal conversion unit (WBSCU) is described. Multiple embedded 8086 and 2901 microprocessors, supported by dedicated hardware modules, perform the required real time operations for both transmit and receive functions. Commands from a host computer determine the configuration of the WBSCU via the IEEE 488 bus. Each of the four WBSCU channels is assigned to process a specified IF waveform; each channel configures its own resources and, in some cases, borrows resources from other channels. The processed waveform data is communicated from individual channels to redundant global memories. Data flow between the user community and global memories occurs via redundant 1553 buses through intelligent Bus Interface Units. Each WBSCU channel contains one 2901 bit slice machine and one 8086 microprocessor. The 2901 provides high speed processing capability for the most time critical operations. The 8086 is used for lower speed processing tasks where its high level language capability can be better exploited. Each 8086 has a global bus for wideband interprocessor communication, and a local bus for 8086/2901, master/slave communication. Software architecture consists of a control and communications structure governing mode dependent signal processing tasks.

Gray, D. M.↗

NASA NTRS1981

Transient upsets in microprocessor controllers

The modeling and analysis of transient faults in microprocessor based controllers are discussed. Such controllers typically consist of a microprocessor, read only memory storing and application program, random access memory for data storage, and input/output devices for external communications. The effects of transient faults on the performance of the controller are reviewed. An instruction level perspective of performance is taken which is the basis of a useful high level program state description of the microprocessor controller. A transition matrix is defined which determines the controller's response to transient fault arrivals.

Glaser, R. E.↗

NASA NTRS1981

Automated mixed traffic transit vehicle microprocessor controller

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

Marks, R. A.↗

NASA NTRS1980

Test vectors development and optimization for a microprocessor

This paper describes a method for generating and optimizing test vectors for a microprocessor, with the aid of a fault simulator implemented entirely by hardware. The development and optimization of test vectors has been done on a tester, with the fault simulator plugged directly into the test head. The fault simulator is capable of automatically injecting over a thousand single or multiple stuck faults in the sequential and combinatorial parts of the microprocessor. The test vectors developed by a programmer working interactively with the tester were applied through the tester to the fault simulator, and the percent of faults detected was measured. The vectors were developed and optimized for the 1802 microprocessor, with the objective of detecting 100% of the single stuck faults with a minimum set of vectors. Experimental results show that 99.7% of the single stuck faults are being detected with approximately 14,000 vectors.

Timoc, C. C.↗

NASA NTRS1983

Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

Dunn, W. R.↗

NASA NTRS1984

The development of a microprocessor-controlled linearly-actuated valve assembly

The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.

Wall, R. H.↗

NASA NTRS1991

Report on the formal specification and partial verification of the VIPER microprocessor

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

Brock, Bishop↗

NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗

NASA NTRS1995

Formal verification of an avionics microprocessor

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

Srivas, Mandayam, K.↗

NASA NTRS1994

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Carson, John C.↗

NASA NTRS2008

Guideline for ground radiation testing of microprocessors in the space radiation environment

The goal of this work is to develop a guideline that is applicable to processors that are potentially useful in space. Thus, the guideline does not consider very high performance processors that are intended for server or high-performance applications where very large amounts of power are tolerated to gain performance because it would be impractical to use such high-power devices in typical space applications. This guide is intended to support insertion of these microprocessors into spaceflight applications and to recommend ground test protocols. The first guideline principle that should be followed is a serious concurrent engineering approach for down selecting space-qualified microprocessors. This requires that the design engineer seek the support of a radiation effects expert who understands total ionizing dose (TID) and single-event effects (SEEs) issues for microprocessors as applied to the system in question.

Irom, Farokh↗

NASA NTRS2004

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

single event upset (SEU)↗

NASA NTRS2004

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

single-event upset (SEU)↗

NASA NTRS1977

Study of limitations and attributes of microprocessor testing techniques

All microprocessor units have a similar architecture from which a basic test philosophy can be adopted and used to develop an approach to test each module separately in order to verify the functionality of each module within the device using the input/output pins of the device and its instruction set; test for destructive interaction between functional modules; and verify all timing, status information, and interrupt operations of the device. Block and test flow diagrams are given for the 8080, 8008, 2901, 6800, and 1802 microprocessors. Manufacturers are listed and problems encountered in testing the modules are discussed. Test equipment and methods are described.

Mccaskill, R.↗