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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Verification and Quantification of Single Event Effects on High Speed SRAM in Terrestrial Environments

As integrated circuits become more sensitive to charged particles and neutrons, anomalous performance due to single event effects (SEE) is a concern and requires experimental verification and quantification. The Center for Applied Radiation Research (CARR) at Prairie View A&M University has developed experiments as a participant in the NASA ER-2 Flight Program, the APEX balloon flight program and the Student Launch Program. Other high altitude and ground level experiments of interest to DoD and commercial applications are being developed. The experiment characterizes the SEE behavior of high speed and high density SRAM's. The system includes a PC-104 computer unit, an optical drive for storage, a test board with the components under test, and a latchup detection and reset unit. The test program will continuously monitor the stored checkerboard data pattern in the SW and record errors. Since both the computer and the optical drive contain integrated circuits, they are also vulnerable to radiation effects. A latchup detection unit with discrete components will monitor the test program and reset the system when necessary. The first results will be obtained from the NASA ER-2 flights, which are now planned to take place in early 1998 from Dryden Research Center in California. The series of flights, at altitudes up to 70,000 feet, and a variety of flight profiles should yield a distribution of conditions for correlating SEES. SEE measurements will be performed from the time of aircraft power-up on the ground throughout the flight regime until systems power-off after landing.

Huff, H.↗
NASA NTRS2008

Analysis of Single-Event Latchup Cross Section in 65 nm SRAMs

Single event latchup (SEL) in a 65 nm CMOS SRAM technology is observed and sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. The significance of these results are discussed and the foundation for a predictive model of SEL is laid out for use with the MRED tool.

Hutson, J. M.↗
NASA NTRS2006

Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

Berg, Melanie↗
NASA NTRS2003

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

SEE testing↗
NASA NTRS2009

Simulation of SRAM SEU Sensitivity at Reduced Operating Temperatures

A new NanoTCAD-to-Spectre interface is applied to perform mixed-mode SEU simulations of an SRAM cell. Results using newly calibrated TCAD cold temperature substrate mobility models, and BSIM3 compact models extracted explicitly for the cold temperature designs, indicate a 33% reduction in SEU threshold for the range of temperatures simulated.

Sanathanamurthy, S.↗
NASA NTRS2018

A First Look at 22 nm FDSOI SRAM Single-Event Test Results

We will present the first ever single-event effects testing results on a 22 nm fully-depleted silicon-on-insulator test chip. The 128 MB SRAMs were irradiated with heavy ions and the results are compared to previous technology generations.

Silicon-on-insulator↗
NASA NTRS1987

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.↗
NASA NTRS1989

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗
NASA NTRS1989

Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

The authors report on an experimental study of dose-induced changes in SEU (single-event-upset) sensitivity of CMOS static RAMs. Two time regimes were investigated following exposure of memories to cobalt-60 gamma rays: the near term, within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze in the damage state until SEU measurements could be made prior to annealing. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46 percent and asymptotic cross sections increased by factors of two to four (unannealed samples).

Stassinopoulos, E. G.↗
NASA NTRS1995

Determination Of LETs Of SRAMs By Use Of A Laser

Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.

Kim, Quiesup↗
NASA NTRS2008

Device-Orientation Effects on Multiple-Bit Upset in 65-nm SRAMs

Heavy ion irradiations have been performed: a) SEU varies little with angle of ion incidence b) MBU depend on the device orientation. The MBU response depends on the well orientation of the device. MRED simulation of an omni-directional GEO environment shows the MBU response to be a combination of response from different orientations. Testing and simulation must account for multiple orientations.

Tipton, Alan D.↗
NASA NTRS2015

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Field Programmable Gate Array (FPGA)↗