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At least 37 records · Page 2

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NASA NTRS2005

Design Study of Wafer Seals for Future Hypersonic Vehicles

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Dunlap, Patrick H.↗

NASA NTRS2006

Performance Evaluations of Ceramic Wafer Seals

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.↗

DOE OSTI2021

System and method for shingling wafer strips connected in parallel

A solar device includes a first string of first solar wafers, wherein a plurality of the first solar wafers each overlap with at least one vertically adjacent solar wafer from the first string. Additionally, the solar device includes a second string of second solar wafers, wherein a plurality of the second solar wafers each overlap with at least one vertically adjacent solar wafer from the second string, wherein a plurality of the first solar wafers overlap with one or more of the plurality of second solar wafers to electrically connect horizontally adjacent solar wafers in parallel.

Caswell, Nathaniel Alexis↗

DOE OSTI2023

System and method for shingling wafer strips connected in parallel

Caswell, Nathaniel↗

DOE OSTI2021

On the in-plane vibrations and electromechanical resonance characteristics of non-uniformly polarized rectangular piezoelectric wafers: Selective mode-type excitation and specific mode enhancement

Here, we investigate the in-plane vibrations and electromechanical resonance characteristics of non-uniformly polarized rectangular piezoelectric wafers. Non-uniform polarization is represented as a non-uniform electromechanical coupling coefficient using a polarization function. Governing equations are derived for the forced in-plane vibrations of a thin wafer under the assumption of generalized plane stress. The effect of non-uniform polarization is explicitly obtained in the forcing terms of the governing equations. These equations are then recast into a variational weak form that is then solved using the finite element method to obtain the displacement fields for different modes. The electromechanical response of a non-uniformly polarized piezoelectric wafer is derived in terms of the out-of-plane displacement profile on the surface of the wafer. Using the derived analytical expression, a necessary and sufficient condition for the presence/absence of a vibrational mode in the electromechanical impedance spectrum is obtained. Based on this condition, criteria for selective mode-type excitation and specific mode enhancement of vibrational modes in the electromechanical impedance spectrum are postulated. Selective mode-type excitation of in-plane extensional and shear modes is demonstrated for a square wafer and that of in-plane bending modes is demonstrated for a rectangular wafer. Specific mode enhancement is demonstrated for both square and rectangular wafers. In addition, it is also demonstrated how the criteria can be used to suppress specific vibrational modes in the electromechanical impedance spectrum. The proposed methodology of using non-uniformly polarized piezoelectric wafers finds application in the design of single element transducers with multi-frequency operation, frequency-tuned receivers/sensors, acoustic holograms, designing acoustic beams of prescribed shape/lobes, and other non-traditional applications such as information storage.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Using machine learning with optical profilometry for GaN wafer screening

Abstract To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

36 MATERIALS SCIENCE↗

DOE OSTI2021

Wafer-level handle replacement

A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.

Meade, Roy Edward↗

DOE OSTI2023

Controlled Growth of Single‐Crystal Graphene Wafers on Twin‐Boundary‐Free Cu(111) Substrates

Single-crystal graphene (SCG) wafers are needed to enable mass-electronics and optoelectronics owing to their excellent properties and compatibility with silicon-based technology. Controlled synthesis of high-quality SCG wafers can be done exploiting single-crystal Cu(111) substrates as epitaxial growth substrates recently. However, current Cu(111) films prepared by magnetron sputtering on single-crystal sapphire wafers still suffer from in-plane twin boundaries, which degrade the SCG chemical vapor deposition. Here, in this study, it is shown how to eliminate twin boundaries on Cu and achieve 4 in. Cu(111) wafers with ≈95% crystallinity. The introduction of a temperature gradient on Cu films with designed texture during annealing drives abnormal grain growth across the whole Cu wafer. In-plane twin boundaries are eliminated via migration of out-of-plane grain boundaries. SCG wafers grown on the resulting single-crystal Cu(111) substrates exhibit improved crystallinity with >97% aligned graphene domains. As-synthesized SCG wafers exhibit an average carrier mobility up to 7284 cm 2 V −1 s −1 at room temperature from 103 devices and a uniform sheet resistance with only 5% deviation in 4 in. region.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Specific resonance mode enhancement and suppression using non-uniform polarization of piezoelectric wafers: Theory and experiments

In this work, we present experimental demonstration of specific resonance mode enhancement and suppression in circular and rectangular piezoelectric wafers with engineered non-uniform polarization profiles. The polarization profiles are designed based on the electromechanical impedance response of non-uniformly polarized wafers as obtained from the theory. The circular wafers are fabricated with non-uniform polarization profiles that involve a central polarized region surrounded by an unpolarized region. The radius of the polarization zone is designed based on the condition for specific mode enhancement obtained from the electromechanical impedance response of non-uniformly polarized wafers. We actually show how the condition can not only be used to enhance but also to suppress electromechanical resonances. Two kinds of wafers are designed and fabricated to specifically suppress second and third radial modes respectively. Similarly, rectangular wafers are designed with two different kinds of non-uniform polarization profiles — the first of which enhances the second in-plane extensional mode in the impedance spectrum and the second polarization profile suppresses all the electromechanical resonances pertaining to the in-plane extensional modes and selectively excites only the in-plane bending modes. The proposed approach of using non-uniformly polarized wafers finds application in designing multi-frequency sensors/transducers, frequency-tuned receivers, acoustic beamforming, and other non-traditional applications such as information storage.

36 MATERIALS SCIENCE↗

DOE OSTI2021

Acoustic Wafer Defect Detection System

Researchers at Los Alamos have developed the Acoustic Wafer Defect Detection System, a technology that enables rapid diagnosis of critical defects during wafer production. This technology is capable of both efficient and accurate detection of defects in wafers, including defects that are undetectable through current optical techniques. The system identifies the wafer defects by exciting resonant vibrations in the wafers and by exciting “crack breathing” modes. These vibrations cause the crack to periodically open and close. Specific resonance characteristics, combined with acoustic signatures resulting from crack breathing, result in a technique that is highly sensitive to cracked wafers. There are minimal custom parts used to build the system, and it can be easily implemented in nearly any wafer production plant with minimal modifications. We are seeking a commercialization partner to license the technology or partner through a Cooperative Research and Development Agreement (CRADA) to develop into a usable product for commercial purposes.

42 ENGINEERING↗

NASA NTRS2002

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Okojie, Robert S.↗

DOE OSTI2022

Temperature and illumination dependence of silicon heterojunction solar cells with a wide range of wafer resistivities

Abstract Recently, the significant improvements in the surface and contact passivation of silicon (Si) solar cells as well as their bulk quality have shifted their operating point to higher injections. Hence, they are less dependent on wafer doping. This shift opens an opportunity of using high‐resistivity wafers for practical photovoltaic applications, introducing a promising approach to push the cell efficiency towards the intrinsic limit and to improve the module reliability by increasing the cell breakdown voltage. Therefore, insights into the performance of Si solar cells using high‐resistivity wafers at various operating temperatures are of significant interest. In this study, we investigate the temperature‐ and illumination‐dependent performance of Si heterojunction (SHJ) solar cells using a wide range of wafer resistivities (between 3 and 1000 Ω⋅cm). Although a reduction in the passivation quality of the passivating contacts is observed at elevated temperature, the impact on the temperature coefficient of the open‐circuit voltage (TC V oc )—the dominant contributor to the temperature coefficient (TC) of the cell efficiency—is very limited. Their TC V oc are still dominated by the temperature dependence of the effective intrinsic carrier concentration. Furthermore, we also find that the investigated cells are more sensitive to temperature variation at lower illumination intensities. It is noteworthy that the efficiency of the cells fabricated using high‐resistivity wafers is comparable to that of the reference cells at any given temperature, highlighting the potential of using high‐resistivity wafers for solar cells.

14 SOLAR ENERGY↗

NASA NTRS1988

Laser furnace and method for zone refining of semiconductor wafers

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Griner, Donald B.↗

NASA NTRS2006

Equipment for On-Wafer Testing From 220 to 325 GHz

A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

Samoska, Lorene↗

NASA NTRS2013

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.↗

NASA NTRS2017

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Park, Yeonjoon↗

DOE OSTI2023

Wafer-Scale Synthesis of 2D Materials by an Amorphous Phase-Mediated Crystallization Approach

The interest in the wafer-scale growth of two-dimensional (2D) materials, including transition metal dichalcogenides (TMDCs), has been rising for transitioning from lab-scale devices to commercial-scale systems. Among various synthesis techniques, physical vapor deposition, such as pulsed laser deposition (PLD), has shown promise for the wafer-scale growth of 2D materials. However, due to the high volatility of chalcogen atoms (e.g., S and Se), films deposited by PLD usually suffer from a lack of stoichiometry and chalcogen deficiency. To mitigate this issue, excess chalcogen is necessary during the deposition, which results in problems like uniformity or not being repeatable. This study demonstrates a condensed-phase or amorphous phase-mediated crystallization (APMC) approach for the wafer-scale synthesis of 2D materials. This method uses a room-temperature PLD process for the deposition and formation of amorphous precursors with controlled thicknesses, followed by a post-deposition crystallization process to convert the amorphous materials to crystalline structures. This approach maintains the stoichiometry of the deposited materials throughout the deposition and crystallization process and enables the large-scale synthesis of crystalline 2D materials (e.g., MoS 2 and WSe 2 ) on Si/SiO 2 substrates, which is critical for future wafer-scale electronics. We show that the thickness of the layers can be digitally controlled by the number of laser pulses during the PLD phase. Optical spectroscopy is used to monitor the crystallization dynamics of amorphous layers as a function of annealing temperature. The crystalline quality, domain sizes, and the number of layers were explored using nanoscale and atomistic characterization (e.g., AFM, STEM, and EDS) along with electrical characterization to explore process–structure–performance relationships. Finally, this growth technique is a promising method that could potentially be adopted in conventional semiconductor industries for wafer-scale manufacturing of next-generation electronic and optoelectronic devices.

2D electronics↗

DOE OSTI2023

High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process

Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III–N and III–V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.

77 NANOSCIENCE AND NANOTECHNOLOGY↗